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參數(shù)資料
| 型號(hào)： | WEDPNF8M721V-1012BC |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| 中文描述： | 8Mx72同步DRAM 8MB閃存的混合模塊多芯片封裝 |
| 文件頁數(shù)： | 17/42頁 |
| 文件大小： | 1276K |
| 代理商： | WEDPNF8M721V-1012BC |
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White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
WEDPNF8M721V-XBX
0. Standard read cycle timings and IFCC read specifications
apply. Refer to “Write Operation Status” for more informa-
tion, and to “Flash AC Characteristics” for timing diagrams.
STANDBY MODE
When the system is not reading or writing to the device, it
can place the device in standby mode. In this mode, cur-
rent consumption is greatly reduced, and the outputs are
placed in the high impedance state, independent of the
FOE input.
The device enters the CMOS standby mode when the FCS
and RST pins are both held at Vcc ±0.3V. (Note that this is
a more restricted voltage range than VIH.) If FCS and RST are
held at VIH, but not within Vcc to ±0.3V the device will
be in the standby mode, but the standby current will be
greater. The device requires standard access time (t
CE
) for
read access when the device is in either of these standby
modes, before it is ready to read data.
If the device is deselected during erasure or programming,
the device draws active current until the operation is com-
pleted.
In the Flash DC Characteristics table, IFCC3 and IFCC4 repre-
sent the standby current specifications.
T
ABLE
5 - B
OTTOM
B
OOT
B
LOCK
S
ECTOR
A
DDRESS
T
ABLE
Sector Size
(Kbytes)
16
8
8
32
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
(x8) Address Range
(In hexidecimal)
00000h-03FFFh
04000h-05FFFh
06000h-07FFFh
08000h-0FFFFh
10000h-1FFFFh
20000h-2FFFFh
30000h-3FFFFh
40000h-4FFFFh
50000h-5FFFFh
60000h-6FFFFh
70000h-7FFFFh
80000h-8FFFFh
90000h-9FFFFh
A0000h-AFFFFh
B0000h-BFFFFh
C0000h-CFFFFh
D0000h-DFFFFh
E0000h-EFFFFh
F0000h-FFFFFh
Sector
SA
0
SA
1
SA
2
SA
3
SA
4
SA
5
SA
6
SA
7
SA
8
SA
9
SA
10
SA
11
SA
12
SA
13
SA
14
SA
15
SA
16
SA
17
SA
18
A
18
18
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
A
17
17
17
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
A
16
16
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A
15
15
15
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
A
14
14
14
0
0
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
A
13
13
0
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
A
12
12
12
X
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
AUTOMATIC SLEEP MODE
The automatic sleep mode minimizes Flash device energy
consumption. The device automatically enables this mode
when addresses remain stable for t
ACC
+ 30 ns. The auto-
matic sleep mode is independent of the FCS, FWE, and FOE
control signals. Standard address access timings provide
new data when addresses are changed. While in sleep
mode, output data is latched and always available to the
system. Ifcc5 in the DC Characteristics table represents the
automatic sleep mode current specification.
RST: HARDWARE RESET PIN
The RST pin provides a hardware method of resetting the
device to reading array data. When the RST pin is driven
low for at least a period of tRP or greater the device imme-
diately terminates any operation in progress, tristates all
output pins, and ignores all read/write commands for the
duration of the RST pulse. The device also resets the inter-
nal state machine to reading array data. The operation that
was interrupted should be reinitiated once the device is
ready to accept another command sequence, to ensure
data integrity.
Current is reduced for the duration of the RST pulse. When
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| WEDPNF8M721V-1012BI | 8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M721V-1012BM | 8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M721V-1015BC | 8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M721V-1015BI | 8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M721V-1015BM | 8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| WEDPNF8M721V-1012BI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M721V-1012BM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M721V-1015BC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M721V-1015BI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M721V-1015BM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
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