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參數資料
| 型號： | MC88915FN70PLCC |
| 廠商： | Motorola, Inc. |
| 英文描述： | Low Skew CMOS PLL Clock Driver |
| 中文描述： | 低偏移的CMOS PLL時鐘驅動器 |
| 文件頁數： | 14/20頁 |
| 文件大小： | 216K |
| 代理商： | MC88915FN70PLCC |
MC88915TFN55/70/100/133/160
MOTOROLA
TIMING SOLUTIONS
BR1333 — Rev 6
14
6.
Calculation of Total Output–to–Skew between
multiple parts (Part–to–Part skew)
By combining the tPD specification and the information in
Note 5, the worst case output–to–output skew between
multiple 88915’s connected in parallel can be calculated.
This calculation assumes that all parts have a common
SYNC input clock with equal delay of that input signal to
each part. This skew value is valid at the 88915 output
pins only (equally loaded), it does not include PCB trace
delays due to varying loads.
With a 1M
resistor tied to analog VCC as shown in note
4, the tPD spec. limits between SYNC and the Q/2 output
(connected to the FEEDBACK pin) are –1.05ns and
–0.5ns. To calculate the skew of any given output
between two or more parts, the absolute value of the
distribution of that output given in table 2 must be
subtracted and added to the lower and upper tPD spec
limits respectively. For output Q2, [276 – (–44)] = 320ps is
the absolute value of the distribution. Therefore
[–1.05ns – 0.32ns] = –1.37ns is the lower tPD limit, and
[–0.5ns + 0.32ns] = –0.18ns is the upper limit. Therefore
the worst case skew of output Q2 between any number of
parts is |(–1.37) – (–0.18)| = 1.19ns. Q2 has the worst
case skew distribution of any output, so 1.2ns is the
absolute worst case output–to–output skew between
multiple parts.
7. Note 4 explains that the tPD specification was measured
and is guaranteed for the configuration of the Q/2 output
connected to the FEEDBACK pin and the SYNC input
running at 10MHz. The fixed offset (tPD) as described
above has some dependence on the input frequency and
at what frequency the VCO is running. The graphs of
Figure 3 demonstrate this dependence.
The data presented in Figure 3 is from devices
representing process extremes, and the measurements
were also taken at the voltage extremes (VCC = 5.25V
and 4.75V). Therefore the data in Figure 3 is a realistic
representation of the variation of tPD.
SYNC INPUT FREQUENCY (MHz)
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
5
10
15
20
25
3.5
3.0
2.5
2.0
1.5
1.0
0.5
2.5
5.0
7.5
10.0
12.5
15.0
17.5
2.5
5.0
7.5
10.0
12.5
15.0
17.5
–0.5
–1.0
–1.5
–2.0
2.5 5.0
7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 27.5
tPD
SYNC to
FEEDBACK
(ns)
SYNC INPUT FREQUENCY (MHz)
Figure 3a.
tPD versus Frequency Variation for Q/2 Output Fed
Back, Including Process and Voltage Variation @ 25
°
C
(With 1M
Resistor Tied to Analog VCC)
–0.50
–0.75
–1.00
–1.25
–1.50
tPD
SYNC to
FEEDBACK
(ns)
tPD
SYNC to
FEEDBACK
(ns)
tPD
SYNC to
FEEDBACK
(ns)
Figure 3b.
tPD versus Frequency Variation for Q4 Output Fed
Back, Including Process and Voltage Variation @ 25
°
C
(With 1M
Resistor Tied to Analog VCC)
Figure 3c.
tPD versus Frequency Variation for Q/2 Output Fed
Back, Including Process and Voltage Variation @ 25
°
C
(With 1M
Resistor Tied to Analog GND)
Figure 3d.
tPD versus Frequency Variation for Q4 Output Fed
Back, Including Process and Voltage Variation @ 25
°
C
(With 1M
Resistor Tied to Analog GND)
SYNC INPUT FREQUENCY (MHz)
SYNC INPUT FREQUENCY (MHz)
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| MC88915TEI100 | 功能描述:IC PLL CLOCK DRIVER 28-PLCC RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發生器，PLL，頻率合成器 系列:- 標準包裝:1,000 系列:- 類型:時鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數:- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應商設備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
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| MC88915TEI133 | 功能描述:IC PLL CLOCK DRIVER 28-PLCC RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發生器，PLL，頻率合成器 系列:- 標準包裝:1,000 系列:- 類型:時鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數:- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應商設備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
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