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TMS320TCI6482
Communications Infrastructure Digital Signal Processor
SPRS246F–APRIL 2005–REVISED MAY 2007
8.7.3.4
PLL Controller Divider 4 Register
The PLL controller divider 4 register (PLLDIV4) is shown in
Figure 8-14
and described in
Table 8-22
.
Besides being used as the EMIFA internal clock, SYSCLK4 is also used in other parts of the system.
Disabling this clock will cause unpredictable system behavior. Therefore, the PLLDIV4 register should
never be used to disable SYSCLK4.
31
16
Reserved
R-0
15
14
5
4
0
D4EN
Reserved
RATIO
R/W-1
LEGEND:
R/W = Read/Write; R = Read only; -
n
= value after reset
R-0
R/W-3
Figure 8-14. PLL Controller Divider 4 Register (PLLDIV4) [Hex Address: 029A 0160]
Table 8-22. PLL Controller Divider 4 Register (PLLDIV4) Field Descriptions
Bit
31:16
15
Field
Reserved
D4EN
Value
0
Description
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
Divider 4 enable bit.
Divider 4 is disabled. No clock output.
Divider 4 is enabled.
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
Divider ratio bits.
÷2. Divide frequency by 2.
÷4. Divide frequency by 4.
÷6. Divide frequency by 6.
÷8. Divide frequency by 8.
÷10 to ÷16. Divide frequency by 10 to divide frequency by 16.
Reserved, do not use.
0
1
0
14:5
4:0
Reserved
RATIO
0-1Fh
0
1h
2h
3h
4h-7h
8h-1Fh
C64x+ Peripheral Information and Electrical Specifications
140
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