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參數(shù)資料
| 型號： | W88112F |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 存儲控制器/管理單元 |
| 英文描述： | ATAPI CD-ROM DECODER & CONTROLLER |
| 中文描述： | IDE COMPATIBLE, CD ROM CONTROLLER, PQFP100 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁數(shù)： | 15/64頁 |
| 文件大小： | 466K |
| 代理商： | W88112F |
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W88111AF/W88112F
Preliminary/Confidential
ATAPI CD-ROM Decoder & Controller
This specification is subject to change without notice.
Publication Release Date: Aug, 1996
Preliminary/ Confidential Revision A0.1
- 15 -
TBCL/TBCH - Transfer Byte/Word Counter - (read/write 02h/03h)
Before triggering data transfer, the number of bytes or words to be transferred should be set through
12-bit Transfer Byte/Word Counter. The number of
bytes
minus 1 should be written to this counter
while using 8-bit data transfer. The number of
words
minus 1 should be written to this counter while
using 16-bit data transfer. After host reads one byte or word, the counter is decreased by one till
Transfer End Interrupt is activated when this counter becomes zero.
TACL/TACH - Transfer Address Counter - (write 04h/05h)
Before triggering data transfer, the external RAM address of data to be transferred should be set
through 16-bit Transfer Address Counter. This number in this counter specifies the first available
data address relative to the beginning of the block. The block number should also be specified
through Transfer Block registers TBL/TBH(24h/25h). After one byte/word is read by host,
TACL/TACH are increased to the next available data address.
TBL/TBH - Transfer Block Register - (read/write 24h/25h)
Before triggering data transfer, the external RAM block of data to be transferred should be set through
Transfer Block Registers. TBL/TBH form a 9-bit register that is used to specify the first RAM block to
be transferred, while TACL/TACH(04h/ 05h) specify the starting address relative to the beginning of
this RAM block. The RAM block number in TBL/TBH is not increased automatically at the end of
each transfer unless multi-block transfer is used by specifying register MBTC0(12h).
THTRG - Transfer to Host Trigger Register - (write 06h)
This register is used to trigger data transfer regardless of what value is written.
When bit UDTS(1Fh.6) is low, the data transfer from external RAM to the host after THTRG is
triggered. Triggering THTRG automatically fills the Data FIFO and then flag DFRDYb(01h.1)
becomes active-low when the Data FIFO becomes ready.
When bit UDTS(1Fh.6) is high, the path of data transfer is from registers DF0-DF7(40h-47h) to the
host. In this case, the data count, less than 8, should be set using registers TBCL(02h) before
triggering THTRG and bit UDTT(1Fh.7) should be set to 1 followed by 0 after triggering THTRG.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| W88113C | ATAPI CD-ROM DECODER & CONTROLLER |
| W88113CD | ATAPI CD-ROM DECODER & CONTROLLER |
| W88113CF | ATAPI CD-ROM DECODER & CONTROLLER |
| W88227F | ATAPI CD-ROM Decoder(支持ATAPI標(biāo)準(zhǔn)的CD-ROM解碼器) |
| W88227QD | ATAPI CD-ROM Decoder(支持ATAPI標(biāo)準(zhǔn)的CD-ROM解碼器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W88113C | 制造商:WINBOND 制造商全稱:Winbond 功能描述:ATAPI CD-ROM DECODER & CONTROLLER |
| W88113CD | 制造商:WINBOND 制造商全稱:Winbond 功能描述:ATAPI CD-ROM DECODER & CONTROLLER |
| W88113CF | 制造商:WINBOND 制造商全稱:Winbond 功能描述:ATAPI CD-ROM DECODER & CONTROLLER |
| W88611P | 制造商:WINBOND 制造商全稱:Winbond 功能描述:VCD 4X RF AMP/DIGITAL SERVO & DSP |
| W88631F | 制造商:WINBOND 制造商全稱:Winbond 功能描述:VCD 4X RF AMP/DIGITAL SERVO & DSP |
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