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參數資料
| 型號： | W88112F |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 存儲控制器/管理單元 |
| 英文描述： | ATAPI CD-ROM DECODER & CONTROLLER |
| 中文描述： | IDE COMPATIBLE, CD ROM CONTROLLER, PQFP100 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁數： | 16/64頁 |
| 文件大小： | 466K |
| 代理商： | W88112F |
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W88111AF/W88112F
Preliminary/Confidential
ATAPI CD-ROM Decoder & Controller
This specification is subject to change without notice.
Publication Release Date: Aug, 1996
Preliminary/ Confidential Revision A0.1
- 16 -
TACK - Transfer Acknowledge - (write 07h)
Writing register TACK deactivates TENDb(01h.6) and its corresponding microprocessor interrupt
regardless of what data is written.
HEAD0 to HEAD3 - Header Registers - (read 03h to 07h)
These four registers are used to hold the information of Header Bytes of each sector. Header
Registers should be read soon after STAVAb(0F.7) becomes active-low. Note that the header bytes
are untrustful if wrong mode is set while ECC is enabled. If the bit SHDEN(0Bh.0) is enabled,
registers HEAD0-3 are used to hold subheader bytes instead.
BIAL/BIAH - Buffering Initial Address Register - (write 08h/09h)
Before enabling the external RAM buffering, BIAL/BIAH should be set to control the location of the
first byte follows data sync for each data sector. The RAM block for buffering is controlled by the
number in registers DDBL/DDBH(28h/29h) plus one. For convenience of following data transfer, the
microprocessor should set proper value to BIAH/BIAL(FF,F0h for mode-1 and FF,E8h for mode-2)
after the mode is determined so that the first user data byte will locate at offset 00h of each data
block.
BACL, BACH - Buffering Address Counter - (read 0Ah/0Bh)
After enabling the external RAM buffering, Buffering Write Counter are automatically increased by
two , beginning from the value specified by BIAL/BIAH, every time a data word is buffered.
EIAL/EIAH - ECC Initial Address Register- (read 08h/09h, write 0Ch/0Dh)
EIAL/EIAH are used to hold the initial address offset of the data block to be corrected. The content of
BIAL/BIAH(08h/09h) will be automatically loaded to EIAL/EIAH at the beginning of each data sync,
making it unnecessary to read or write EIAL/EIAH during normal operation. The RAM block for ECC
is controlled by the number in registers DDBL/DDBH(28h/29h).
相關PDF資料 |
PDF描述 |
|---|---|
| W88113C | ATAPI CD-ROM DECODER & CONTROLLER |
| W88113CD | ATAPI CD-ROM DECODER & CONTROLLER |
| W88113CF | ATAPI CD-ROM DECODER & CONTROLLER |
| W88227F | ATAPI CD-ROM Decoder(支持ATAPI標準的CD-ROM解碼器) |
| W88227QD | ATAPI CD-ROM Decoder(支持ATAPI標準的CD-ROM解碼器) |
相關代理商/技術參數 |
參數描述 |
|---|---|
| W88113C | 制造商:WINBOND 制造商全稱:Winbond 功能描述:ATAPI CD-ROM DECODER & CONTROLLER |
| W88113CD | 制造商:WINBOND 制造商全稱:Winbond 功能描述:ATAPI CD-ROM DECODER & CONTROLLER |
| W88113CF | 制造商:WINBOND 制造商全稱:Winbond 功能描述:ATAPI CD-ROM DECODER & CONTROLLER |
| W88611P | 制造商:WINBOND 制造商全稱:Winbond 功能描述:VCD 4X RF AMP/DIGITAL SERVO & DSP |
| W88631F | 制造商:WINBOND 制造商全稱:Winbond 功能描述:VCD 4X RF AMP/DIGITAL SERVO & DSP |
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