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參數資料
| 型號： | W88113CF |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 存儲控制器/管理單元 |
| 英文描述： | ATAPI CD-ROM DECODER & CONTROLLER |
| 中文描述： | IDE COMPATIBLE, CD ROM CONTROLLER, PQFP100 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁數： | 18/102頁 |
| 文件大?。?/td> | 573K |
| 代理商： | W88113CF |
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W88113C
Publication Release Date: Mar. 1999
- 14 - Revision 0.61
Bits 4, 3, 2: Reserved
Bit 1:
DTEN - Data Transfer Enable
Set this bit high enables the data transfer logic. This bit should be set before trigger any data
transfer. In order to reduce the interference of microprocessor, this bit is also automatically
enabled during the following operation:
Trigger
ADTT (17h.w2)
Host issues ATAPI Packet Command (A0h) while
APKTEN (18h.7)
is enabled and drive is
selected
In case of un-recoverable transfer error, setting this bit low will terminate the current data
transfer immediately.
Bit 0: Reserved
INTREA - Interrupt Reason Register - (read 01h)
Bit 7:
PFNEb - Packet FIFO Not Empty Interrupt Flag
This bit becomes active-low after Packet FIFOs receive any data issued by the host through
ATAPI Data port.
Pin UINTb (36)
is activated when this bit becomes active-low if
PFNEEN
(01h.w7)
is enabled. This flag is deactivated after the last byte is read by microprocessor
through register
PFAR (00h,r)
.
Bit 6:
TENDb - Transfer End Interrupt Flag
This bit becomes active-low at the end of data transfers. Flag
TDIR (30h.r5)
and
FPKT
(30h.r1)
can be used to determine which type of transfer end occurs.
Pin UINTb (36)
is
activated when this bit becomes active-low if
TENDEN (01h.w6)
is enabled.
TENDb
(01h.r6)
TDIR
(30h.r5)
FPKT
(30h.1)
Transfer End Reason
Acknowledge register
0
1
0
data-in transfer
DHTACK (0Eh), TACK (07h)
0
1
x
data-out transfer
TACK (07h)
0
0
x
A0 command packet transfer
TACK (07h)
Bit 5:
SRIb - Sector Ready Interrupt Flag
If
RMSRI (5Ch.0)
is low, this bit is used to indicate that one sector is ready to be accessed. If
RMSRI (5Ch.0)
is high, this bit is generated only by
STAERR (80h.r6)
,
BIN0 (80h.r5), DSFULI
(80h.r4)
,
LASTBK (80h.r3)
,
LTTI (80h.r2)
,
TNFI (80h.r1)
or
HCEI (80h.r0)
.
Reading register
STAT3 (0Fh,r)
,
LSTA3 (4Bh,r)
or
TARSTA (80h,r)
deactivates this flag.
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