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參數資料
| 型號： | W88113CF |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 存儲控制器/管理單元 |
| 英文描述： | ATAPI CD-ROM DECODER & CONTROLLER |
| 中文描述： | IDE COMPATIBLE, CD ROM CONTROLLER, PQFP100 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁數： | 55/102頁 |
| 文件大小： | 573K |
| 代理商： | W88113CF |
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W88113C
Publication Release Date: Mar. 1999
- 51 - Revision 0.61
Ring Control Registers - (read/write 50h to 57h)
These eight registers add flexibility to the block control of external memory that is controlled by
RTC2-0 (2Ah.2-0)
initially. Once one of these eight registers is set, all eight registers should be set to
take full control of block configuration of the external memory. The data-transfer-ring and write-
buffer-ring are normally set the same value.
DTRBL/DTRBH - Data Transfer Ring Base Register - (read/write 50h/51h)
Data Transfer Ring Base Register and Data Transfer Ring Ceiling Register treat the external memory
as a ring while transferring data to the host. Data Transfer Ring Base Register specifies the base
block number of this ring.
DTRCL/DTRCH - Data Transfer Ring Ceiling Register - (read/write 52h/53h)
Data Transfer Ring Base Register and Data Transfer Ring Ceiling Register treat the external memory
as a ring while transferring data to the host. Data Transfer Ring Base Register specifies the ceiling
block number of this ring. The first block to be transferred is specified by registers
TBH/L (25h/24h)
.
The further data transfer after the end of Data Transfer Ceiling block will access data in Data Transfer
Base block.
WBRBL/WBRBH - Write Buffer Ring Base Register - (read/write 54h/55h)
Write Buffer Ring Base Register and Write Buffer Ring Ceiling Register treats the external memory
as a ring while buffering the serial data from DSP. Write Buffer Ring Base Register specifies the
base block number of this ring.
WBRCL/WBRCH - Write Buffer Ring Ceiling Register - (read/write 56h/57h)
Write Buffer Ring Base Register and Write Buffer Ring Ceiling Register treats the external memory
as a ring while buffering the serial data from DSP. Write Buffer Ring Base Register specifies the
base block number of this ring. The first block to be buffered is specified by registers
DDBH/L
(29h/28h)
. Further serial data buffering after the end of Write Buffer Ceiling block will buffer serial
data into the Write Buffer Base block.
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