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參數資料
| 型號： | W88113CF |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 存儲控制器/管理單元 |
| 英文描述： | ATAPI CD-ROM DECODER & CONTROLLER |
| 中文描述： | IDE COMPATIBLE, CD ROM CONTROLLER, PQFP100 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁數： | 26/102頁 |
| 文件大小： | 573K |
| 代理商： | W88113CF |
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W88113C
Publication Release Date: Mar. 1999
- 22 - Revision 0.61
DHTACK - DRAM to Host Transfer Acknowledge - (write 0Eh)
Writing DHTACK, regardless of what data is written, deactivates
TENDb (01h.r6)
that caused by data-
in transfer.
STAT2 - Status Register 2 - (read 0Eh)
Bit 7-4: RMOD[3:0] - Raw Mode Bit
RMOD2-0 are directly latched from bit 2-0 from the 4th header byte and RMOD3 is high if
any one of the other 5 bits in the mode byte is high. RMOD3 is also high if a mode byte
erasure is detected.
Bit 3:
MODE2 - Mode 2 Selected Flag
This bit reflects the setting of
M2RQ (0Bh.w3)
.
Bit 2:
NOCOR - No Correction
If ECC logic is enabled by bit
EDCEN (0Ah.w5)
, and
QCEN (0Ah.w1)
or
PCEN (0Ah.w0)
, this
bit becomes high if ECC logic is interrupted the followings:
CWEN (0Bh.w4)
is disabled.
Mode mismatch is detected while
MCRQ (0Bh.w1)
is enabled.
Mode erasure is detected while
MCRQ (0Bh.w1)
is enabled. A mode erasure occurs if the
incoming C2PO flag is set for the fourth header byte, indicating unreliable mode data.
Form 2 enabled while ECC logic is set to mode 2. Form 2 blocks should not be corrected.
Form 2 can be enabled by control bit
F2RQ (0Bh.w2),
or by the Form bit in the Subheader
byte if
ACEN (0Ah.w4)
is enabled.
Form bit erasure while ECC logic is set to mode 2 and ACEN is enabled. A form bit
erasure is detected if the incoming C2PO flags are set for both Form bits in the Subheader
bytes.
ILSYN (0Ch.r6)
becomes high while
SDEN (0Bh.w6)
is enabled
Bit 1:
RFERA - Raw Form Erasure
This bit becomes high when a form bit erasure was detected. A form bit erasure is detected if
the incoming C2PO flags are set for both Form bits in the Submode bytes (bit 5 in byte 18
and 22). RFERA becomes valid when
SRIb (01h.r5)
becomes active-low, and remains valid
until the next block sync.
Bit 0:
RFORM - Raw Form Bit
This bit is high if the Form bit is high in the Submode bytes of the incoming serial data.
RFORM becomes valid when flag
SRIb (01h.r5)
becomes active-low, and remains valid until
the next block sync.
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