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參數(shù)資料
| 型號： | W89C840AF |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 100/10Mbps Ethernet Controller |
| 中文描述： | 1 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP128 |
| 封裝： | PLASTIC, QFP-128 |
| 文件頁數(shù)： | 47/82頁 |
| 文件大小： | 918K |
| 代理商： | W89C840AF |
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W89C840AF
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47
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Publication Release Date:October 2000
Revision 1.01
31:0
W
TSD
Transmit Start Demand
A write to this register will trigger the W89C840AF
DMA to fetch the descriptor for progressing the transmission
operation when the W89C840AF
the suspend state. Otherwise, the write operation will have no
effect.
transmit
transmit DMA is staying at
The W89C840AF
state if no descriptor is available. Meanwhile, the bit 2 of
C14/CISR will be asserted to claim the transmit buffer
unavailable
transmit DMA will return to the suspend
If there is any descriptor available, W89C840AF will start to the
transmit process.
C08/CRSDR Receive Start Demand Register
The register C04/CTSDR is used to request the W89C840AF to do a receive process.
Bit
Attribute
Bit name
Description
31:0
W
RSD
Receive Start Demand
A write to this register will trigger the W89C840AF
DMA to fetch the descriptor for progressing the receiving
operation when the W89C840AF
the suspend state. Otherwise, the write operation will have no
effect.
receive
receive DMA is staying at
The W89C840AF
state if no descriptor is available. Meanwhile, the bit 7 of
C14/CISR will be asserted to claim the receive buffer
unavailable.
receive DMA will return to the suspend
If there is any descriptor available, W89C840AF will start to the
receive process and waiting for the incoming frames.
C0C/CRDLA Receive Descriptors List Addresses
The register C0C/CRDLA defines the start address of the receive descriptor list. It should be updated only when
the receive DMA state machine is staying at the stop state.
Bit
Attribute
Bit name
Description
31:2
R/W
SRL
Start of Receive List.
1:0
R/W
MBZ
Must be written as 0 for long word alignment.
C10/CTDLA Transmit Descriptors List Addresses
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