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參數資料
| 型號： | W89C982 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | INTEGRATED MULTIPLE REPEATER II |
| 中文描述： | 集成的多中繼二 |
| 文件頁數： | 16/28頁 |
| 文件大?。?/td> | 277K |
| 代理商： | W89C982 |
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Preliminary W89C982AF
- 16 -
lockup and fragment extension logic will inhibit the encoder/transmitter logic when the retransmitted
packet is more than 65536 bits in length.
Packet repetition and network collision handling are performed by the main state machine according
to IEEE specifications. Soon after the network port receiving data packet has been identified, the
main state machine enables the preamble/jam generator to generate a preamble pattern onto the
encoder/transmitter. While the preamble is being transmitted, the received data are still being
monitored. The main state machine will enable the FIFO control logic to read the valid data into the
FIFO when the start of frame delimiter "SFD" is detected. A 1011 bit pattern is filled into the FIFO
before the SFD is detected. Removal of the FIFO data begins after a 60-bit preamble pattern has
been sent.
Inter-IMPR II Interface
The inter-IMPR II interface are designed for large hub applications. The inter-IMPR II interface allows
a minimum of four IMPR IIs to be integrated together to implement a hub with 32 twisted pair line
ports and four AUI ports. An external integrator is needed to handle the IMPR IIs. The data transfers
on the inter-IMPR II interface are in NRZ format and certain signals are used to indicate the network
status. Signals included on the inter-IMPR II interface allow the IMPR IIs to cooperate with each other
in an appropriate manner. Those signals include IDAT, IDCLK, IJAM,
ICRS
,
IBEN
, and
ICOL
. The
ICRS
,
IBEN
,
ICOL
, IJAM, are the control signals. The IDAT and IDCLK are used to transmit or
receive data when the IMPR II asserts
ICRS
and the external integrator asserted
IBEN
and
deasserted
ICOL
to each IMPR II. The IDAT and IDCLK transmit data and a 10 MHz clock to the
IMPR II integrator. When the IMPR II has not asserted
ICRS
and the integrator has asserted
IBEN
and deasserted
ICOL
to each IMPR II , the IMPR II receives the data and a 10 MHz clock from IDAT
and IDCLK. When IJAM is asserted, it indicates that a single port collision (IDAT = 1) or a multiport
collision (IDAT = 0) is occurring.
982Ab
982Ac
ICRSBa
X1a
X1b
X1c
IMPR II Integrator
IBENBa,
ICOLBa
IDATa,
IDCLKa,
IJAMa
ICRSBb
IBENBb,
ICOLBb
IDATb,
IDCLKb,
IJAMb
ICRSBc
IBENBc,
ICOLBc
IDATc,
IDCLKc,
IJAMc
982Aa
The figure above depicts an inter-IMPR II application circuit. The circuit requires an external inter
IMPR II integrator. The external integrator integrated the
ICRS
signal from each IMPR II and
generates signals,
IBEN
and
ICOL
, to the IMPR II. Each IMPR II checks
IBEN
,
ICOL
to handle the
IDAT, IDCLK, IJAM signal direction.
Note that the inter-IMPR II uses different clocks source (X1a, X1b, X1c, etc.) to construct a large scale repeater application.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| W89C982AF | 制造商:WINBOND 制造商全稱:Winbond 功能描述:INTEGRATED MULTIPLE REPEATER II |
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