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參數資料
| 型號： | W89C982 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | INTEGRATED MULTIPLE REPEATER II |
| 中文描述： | 集成的多中繼二 |
| 文件頁數： | 5/28頁 |
| 文件大小： | 277K |
| 代理商： | W89C982 |
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Preliminary W89C982AF
Publication Release Date: November 1996
- 5 -
Revision A1
Continued
INTER-IMPR II INTERFACE PINS
NAME
NO.
39
I/O
I
DESCRIPTION
IBEN
Inter-IMPR II interface Enable:
IBEN
is driven by HUB integrator. The integrator will drive the
IBEN
low if there is only one IMPR II which outputs
ICRS
to the
inter-IMPR II interface. The IMPR II that asserts
ICRS
will be
allowed to transmit valid messages to the IMPR II integrator when
IBEN
is low.
ICOL
40
I
Inter-IMPR II Collision:
ICOL
will be driven low when more than one IMPR II
simultaneously output
ICRS
to the IMPR II integrator. The IMPR II
will not transmit any data to the IMPR II integrator when
ICOL
is
low. On this situation the collision messages will still be sent to all
ports of the IMPR II.
Inter-IMPR II Data Clock:
IDCLK will drive a 10 MHz clock output when
ICRS
is asserted
and
IBEN
is driven. If
ICRS
is not asserted and
IBEN
is driven,
IDCLK will be driven by the IDCLK signal of another IMPR II. If a
dumb hub is used, i.e., no
IBEN
is present, this pin is in high
impedance. This pin is synchronous to IDAT data.
Inter-IMPR II Data:
The IMPR II sends/receives valid packets or inter-port collision
messages to/from other IMPR IIs through the IDAT pin in NRZ
format. IDAT is in high-Z state during inter-IMPR II collisions or
when the network is idle. IDAT remains high when there is a
transmit collision in the IMPR II.
Inter-IMPR II IJAM:
IJAM is driven low when a valid packet is being sent. IJAM is
driven high when IDAT carries a collision message (i.e., always
high or always low). IDAT = 0 indicates a multiport collision and
IDAT = 1 indicates a single port collision condition.
During inter-IMPR II collisions or when the network is idle, IJAM
should be in high-Z state.
MANAGEMENT BUS PINS
IMPR II Reset:
The IMPR II will be forced into its initial state when RST is driven
low.
Management Bus Clock:
The management data are clocked by MCLK serially. The rising
edge of MCLK will latch the data into or out of the IMPR II.
IDCLK
44
I
O
IDAT
45
I
O
Z
IJAM
42
I
O
Z
RST
38
I
MCLK
28
I
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