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參數(shù)資料
| 型號： | W963L6ABN80I |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | SRAM |
| 英文描述： | GT 3C 3#4 PIN PLUG |
| 中文描述： | 512K X 16 PSEUDO STATIC RAM, 75 ns, PBGA48 |
| 封裝： | 8 X 10 MM, 0.75 MM PITCH, TFBGA-48 |
| 文件頁數(shù)： | 6/30頁 |
| 文件大小： | 1028K |
| 代理商： | W963L6ABN80I |
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W963L6ABN
7. FUNCTION TRUTH TABLE
MODE
NOTE
CE2
CE1
WE
OE
LB
UB
A0-18
DQ1-8
DQ9-16
I
DD
DATA
RETENTION
Standby
(Deselect)
Power Down
Program
Output
Disable
X
X
X
X
X
High-Z
High-Z
I
DDS
Yes
*1
H
X
X
X
X
KEY
*6
High-Z
High-Z
No
*2
H
H
X
X
*7
High-Z
High-Z
No Read
H
H
Valid
High-Z
High-Z
Read
*3
H
L
L *5
Valid
Output
Valid
Output
Valid
Input
Valid
Write (Upper Byte)
H
L
Valid
Invalid
Write (Lower Byte)
L
H
Valid
Input
Valid
Input
Valid
Invalid
Write (Word)
H
L
L
H
L
L
Valid
Input
Valid
I
DDA
Yes
Power Down
*4
L
X
X
X
X
X
X
High-Z
High-Z
I
DDP
No/Yes
Notes
: L = V
IL
, H = V
IH
, X can be either V
IL
or V
IH
, High-Z = High impedance, KEY = Key Address.
*1: The Power Down Program can be performed one time after compliance of Power-up timings and it should not be re-
programmed after regular Read or Write.
*2: Output Disable mode should not be kept longer than 1
μ
S.
*3: Byte control at Read mode is not supported.
*4: Power Down mode can be entered from Standby state and all DQ pins are in High-Z state. I
DDP
current and data
retention depend on the selection of Power Down Program.
*5: Either or both
LB
and
UB must be Low for Read operation.
*6: See “Power Down Program Key Table” in next page for details.
*7: Can be either V
IL
or V
IH
but must be valid before Read or Write.
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相關代理商/技術參數(shù) |
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| W964B6BBN | 制造商:WINBOND 制造商全稱:Winbond 功能描述:1M WORD X 16BIT LOW POWER PSEUDO SRAM |
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| W964B6BBN70E | 制造商:WINBOND 制造商全稱:Winbond 功能描述:1M WORD X 16BIT LOW POWER PSEUDO SRAM |
| W964B6BBN70O | 制造商:WINBOND 制造商全稱:Winbond 功能描述:1M WORD X 16BIT LOW POWER PSEUDO SRAM |
| W964B6BBN80 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:1M WORD X 16BIT LOW POWER PSEUDO SRAM |
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