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| 型號： | KMC8113TMP4800V |
| 廠商： | Freescale Semiconductor |
| 文件頁數： | 32/44頁 |
| 文件大小： | 0K |
| 描述： | IC DSP 300/400MHZ 431FCPGA |
| 標準包裝： | 2 |
| 系列： | StarCore |
| 類型： | SC140 內核 |
| 接口： | 以太網，I²C，TDM，UART |
| 時鐘速率： | 400MHz |
| 非易失內存： | 外部 |
| 芯片上RAM： | 1.436MB |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 1.10V |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 431-BFBGA，FCBGA |
| 供應商設備封裝： | 431-FCPBGA（20x20） |
| 包裝： | 托盤 |
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MSC8113 Tri-Core Digital Signal Processor Data Sheet, Rev. 1
Hardware Design Considerations
Freescale Semiconductor
38
3
Hardware Design Considerations
The following sections discuss areas to consider when the MSC8113 device is designed into a system.
3.1
Use the following guidelines for start-up and power-down sequences:
Assert PORESET and TRST before applying power and keep the signals driven low until the power reaches the
required minimum power levels. This can be implemented via weak pull-down resistors.
CLKIN
can be held low or allowed to toggle during the beginning of the power-up sequence. However, CLKIN must
start toggling before the deassertion of PORESET and after both power supplies have reached nominal voltage levels.
If possible, bring up VDD/VCCSYN and VDDH together. If it is not possible, raise VDD/VCCSYN first and then bring up
VDDH. VDDH should not exceed VDD/VCCSYN until VDD/VCCSYN reaches its nominal voltage level. Similarly, bring both
voltage levels down together. If that is not possible reverse the power-up sequence, with VDDH going down first and
then VDD/VCCSYN.
Note:
This recommended power sequencing for the MSC8113 is different from the MSC8102.
External voltage applied to any input line must not exceed the I/O supply VDDH by more than 0.8 V at any time, including during
power-up. Some designs require pull-up voltages applied to selected input lines during power-up for configuration purposes.
This is an acceptable exception to the rule. However, each such input can draw up to 80 mA per input pin per device in the
system during start-up.
After power-up, VDDH must not exceed VDD/VCCSYN by more than 2.6 V.
3.2
When implementing a new design, use the guidelines described in the MSC8113 Design Checklist (AN3374 for optimal system
performance. MSC8122 and MSC8126 Power Circuit Design Recommendations and Examples (AN2937) provides detailed
design information.
Figure 33 shows the recommended power decoupling circuit for the core power supply. The voltage regulator and the
decoupling capacitors should supply the required device current without any drop in voltage on the device pins. The voltage on
the package pins should not drop below the minimum specified voltage level even for a very short spikes. This can be achieved
by using the following guidelines:
For the core supply, use a voltage regulator rated at 1.1 V with nominal rating of at least 3 A. This rating does not
reflect actual average current draw, but is recommended because it resists changes imposed by transient spikes and has
better voltage recovery time than supplies with lower current ratings.
Decouple the supply using low-ESR capacitors mounted as close as possible to the socket. Figure 33 shows three
capacitors in parallel to reduce the resistance. Three capacitors is a recommended minimum number. If possible, mount
at least one of the capacitors directly below the MSC8113 device.
Figure 33. Core Power Supply Decoupling
+
-
Power supply
or
Voltage Regulator
High frequency capacitors
(very low ESR and ESL)
Bulk/Tantalum capacitors
with low ESR and ESL
MSC8113
Maximum IR drop
of 15 mV at 1 A
Note: Use at least three capacitors.
Lmax = 2 cm
One 0.01 F capacitor
for every 3 core supply
(Imin = 3 A)
pads.
1.1 V
Each capacitor must be at least 150
μF.
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