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參數資料
| 型號： | KMC8113TMP4800V |
| 廠商： | Freescale Semiconductor |
| 文件頁數： | 8/44頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DSP 300/400MHZ 431FCPGA |
| 標準包裝： | 2 |
| 系列： | StarCore |
| 類型： | SC140 內核 |
| 接口： | 以太網，I²C，TDM，UART |
| 時鐘速率： | 400MHz |
| 非易失內存： | 外部 |
| 芯片上RAM： | 1.436MB |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 1.10V |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 431-BFBGA，FCBGA |
| 供應商設備封裝： | 431-FCPBGA（20x20） |
| 包裝： | 托盤 |
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MSC8113 Tri-Core Digital Signal Processor Data Sheet, Rev. 1
Electrical Characteristics
Freescale Semiconductor
16
The following sections include illustrations and tables of clock diagrams, signals, and parallel I/O outputs and inputs. When
systems such as DSP farms are developed using the DSI, use a device loading of 4 pF per pin. AC timings are based on a 20 pF
load, except where noted otherwise, and a 50
Ω transmission line. For loads smaller than 20 pF, subtract 0.06 ns per pF down
to 10 pF load. For loads larger than 20 pF, add 0.06 ns for SIU/Ethernet/DSI delay and 0.07 ns for GPIO/TDM/timer delay.
When calculating overall loading, also consider additional RC delay.
2.5.1
Output Buffer Impedances
2.5.2
Start-Up Timing
Starting the device requires coordination among several input sequences including clocking, reset, and power. Section 2.5.3
describes the clocking characteristics. Section 2.5.4 describes the reset and power-up characteristics. You must use the
following guidelines when starting up an MSC8113 device:
PORESET
and TRST must be asserted externally for the duration of the power-up sequence. See Table 11 for timing.
If possible, bring up the VDD and VDDH levels together. For designs with separate power supplies, bring up the VDD
CLKIN
should start toggling at least 16 cycles (starting after VDDH reaches its nominal level) before PORESET
CLKIN
must not be pulled high during VDDH power-up. CLKIN can toggle during this period.
The following figures show acceptable start-up sequence examples. Figure 6 shows a sequence in which VDD and VDDH are
raised together. Figure 7 shows a sequence in which VDDH is raised after VDD and CLKIN begins to toggle as VDDH rises.
Table 6. Output Buffer Impedances
Output Buffers
Typical Impedance (
Ω)
System bus
50
Memory controller
50
Parallel I/O
50
Note:
These are typical values at 65°C. The impedance may vary by ±25% depending on device process and operating temperature.
Figure 6. Start-Up Sequence: VDD and VDDH Raised Together
Vo
lt
a
g
e
Time
o.5 V
3.3 V
1.1 V
VDDH Nominal Level
PORESET/TRST Asserted
VDD Nominal Level
CLKIN Starts Toggling
VDD/VDDH Applied
PORESET/TRST Deasserted
1
2.2 V
VDDH = Nominal Value
VDD = Nominal Value
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