- 您現在的位置：買賣IC網 > PDF目錄363913 > WEDPNF8M721V-1015BI (Electronic Theatre Controls, Inc.) 8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package PDF資料下載
參數資料
| 型號： | WEDPNF8M721V-1015BI |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| 中文描述： | 8Mx72同步DRAM 8MB閃存的混合模塊多芯片封裝 |
| 文件頁數： | 16/42頁 |
| 文件大小： | 1276K |
| 代理商： | WEDPNF8M721V-1015BI |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁當前第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁
16
White Electronic Designs Corporation Phoenix AZ (602) 437-1520
White Electronic Designs
WEDPNF8M721V-XBX
Bypass mode, only two write cycles are required to pro-
gram a byte, instead of four.
An erase operation can erase one sector, multiple sectors,
or the entire device. Table 5 indicates the address space
that each sector occupies. A “sector address” consists of
the address bits required to uniquely select a sector. The
“Flash Command Definitions” section has details on erasing
a sector or the entire chip, or suspending/resuming the erase
operation.
After the system writes the autoselect command sequence,
the device enters the autoselect mode. The system can then
read autoselect codes from the internal register (which is
separate from the memory array) on FD7-0. Standard read
cycle timings apply in this mode. Refer to the "Autoselect
Mode" and "Autoselect Command Sequence" sections for
more information.
IFCC2 in the DC Characteristics table represents the active
current specifications for the write mode. The “Flash AC
Characteristics” section contains timing specification tables
and timing diagrams for write operations.
PROGRAM AND ERASE OPERATION
STATUS
During an erase or program operation, the system may check
the status of the operation by reading the status bits on FD7-
The internal state machine is set for reading array data upon
device power-up, or after a hardware reset. This ensures
that not spurious alteration of the memory content occurs
during the power transition. No command is necessary in
this mode to obtain array data. Standard microprocessor
read cycles that assert valid addresses on the device data
outputs. The device remains enabled for read access until
the command register contents are altered.
See “Reading Array Data” for more information. Refer to the
Flash AC Read-only Operations table for timing specifica-
tions and to Figure 11 for the timing diagram. IFCC1 in the
ICC Specifications and Conditions table represents the ac-
tive current specification for reading array data.
WRITE COMMANDS/COMMAND
SEQUENCES
To writes a command or command sequence (which in-
cludes programming data to the device and erasing sec-
tors of memory), the system must drive FWE and FCS to VIL,
and FOE to VIH.
For program operations, the BYTE1 pin determines whether
the device accepts program data in bytes or words. Refer
to “Word/Byte Configuration” for more information.
The device features an Unlock Bypass mode to facilitate
faster programming. Once the device enters the Unlock
T
ABLE
4 - D
EVICE
B
US
O
PERATIONS
LEGEND:
L = Logic Low = VIL
H = Logic High = VIH
VID = 12.0 ± 0.5V
NOTES:
1. The sector protect and sector unprotect functions may also be mplemented via programming equipment. See the "Sector Protection/Unprotection" section.
2. Addresses are FA18: FA0 n word mode (BYTE1 = V
IH
), FA18: FA-1 n byte mode (BYTE1 = V
IL
)
X = Don’t Care
FAIN = Flash Address n
FDIN = Flash Data n
FDOUT = Flash Data Out
FD
8-15
Operation
FCS
FOE
FWE
RST
Addresses (2)
FD
0-7
BYTE1
= V
FD
OUT
BYTE1
IL
IH
=V
Read
L
L
H
H
FA
IN
FD
OUT
FD
8-14
= High Z
Write
L
H
L
H
FA
IN
FD
OUT
FD
OUT
FD
15
= FA-
1
Standby
Vcc ±0.3V
X
X
Vcc ± 0.3V
X
High Z
High Z
High Z
Output Disable
L
H
H
H
X
High Z
High Z
High Z
Reset
X
X
X
L
X
High Z
High Z
High Z
Sector Address,
FA
6
= L, FA
1
= H,
FA
0
= L
Sector Protect (1)
L
H
L
V
ID
FD
IN
X
X
Sector Address,
FA
6
= H, FA
1
= H,
FA
0
= L
Sector Unprotect (1)
L
H
L
V
ID
FD
IN
X
X
Temporary Sector Unprotect
X
X
X
V
ID
A
IN
FD
IN
FD
IN
High Z
相關PDF資料 |
PDF描述 |
|---|---|
| WEDPNF8M721V-1015BM | 8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M721V-1210BC | 8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M721V-1210BI | 8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M721V-1210BM | 8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M721V-1212BI | 8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
相關代理商/技術參數 |
參數描述 |
|---|---|
| WEDPNF8M721V-1015BM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M721V-1210BC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M721V-1210BI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M721V-1210BM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M721V-1212BC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
發布緊急采購，3分鐘左右您將得到回復。