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White Electronic Designs Corporation Phoenix AZ (602) 437-1520
White Electronic Designs
WEDPNF8M721V-XBX
DC E
LECTRICAL
C
HARACTERISTICS
A
ND
O
PERATING
C
ONDITIONS
(N
OTES
1, 3)
(VCC = +3.3V ±0.3V; TA = -55°C
TO
+125°C)
Parameter/Condition
Symbol
Units
Min
3
Max
3.6
Supply Voltage
V
CC
V
Input High Voltage: Logic 1; All nputs (4)
V
IH
0.7 x Vcc
V
CC
+ 0.3
V
Input Low Voltage: Logic 0; All nputs (4)
V
IL
-0.3
0.8
V
SDRAM
Input Leakage Current: Any input 0V
≤
V
IN
≤
V
CC
(All other pins not under test = 0V)
I
I
-5
5
μA
SDRAM nput Leakage Address Current
(All other pins not under test = 0V)
I
I
-25
25
μA
SDRAM Output Leakage Current: I/Os are disabled; 0V
≤
V
OUT
≤
V
CC
SDRAM Output High Voltage (I
OUT
= -4mA)
I
OZ
-5
5
μA
V
OH
2.4
–
V
SDRAM Output Low Voltage (I
OUT
= 4mA)
V
OL
–
0.4
V
Flash
Flash Input Leakage Current (V
CC
= 3.6, V
IN
= GND or V
CC)
I
LI
10
μA
Flash Output Leakage Current (V
CC
= 3.6, V
IN
= GND or V
CC)
I
LOx8
10
μA
Flash Output High Voltage (I
OH
= -2.0 mA, V
CC
= 3.0)
V
OH1
0.85
X
V
CC
V
Flash Output Low Voltage (I
OL
= 5.8 mA, V
CC
= 3.0)
V
O
L
0.45
V
Flash Low V
CC
Lock-Out Voltage (5)
V
LKO
2.3
2.5
V
A
BSOLUTE
M
AXIMUM
R
ATINGS
Parameter
Supply Voltage Range (V
CC
)
Signal Voltage Range
Operating Temperature T
A
(Mil)
Operating Temperature T
A
(Ind)
Storage Temperature, Plastic
Flash Endurance (write/erase cycles)
NOTE:
Stress greater than those isted under "Absolute Maximum Ratings" may cause
permanent damage to the device. This s a stress rating only and functional
operation of the device at these or any other conditions greater than those
indicated n the operational sections of this specification s not mplied.
Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
Unit
V
V
°C
°C
°C
cycles
-0.5 to +4.0
-0.5 to Vcc +0.5
-55 to +125
-40 to +85
-65 to +150
1,000,000 min.
SDRAM C
APACITANCE
(N
OTE
2)
Parameter
Input Capacitance: CLK
Addresses, BA
0-1
Input Capacitance
Input Capacitance: All other nput-only pins
Input/Output Capacitance: /Os
Symbol
C
I1
C
A
C
I2
C
IO
Max
10
35
10
12
Unit
pF
pF
pF
pF
F
LASH
D
ATA
R
ETENTION
Parameter
Test Conditions
Min
Unit
Minimum Pattern Data
Retention Time
150°C
125°C
10
20
Years
Years
NOTES:
1. All voltages referenced to VSS.
2. This parameter s not tested but guaranteed by design. f = 1 MHz, TA = 25°C.
3. An nitial pause of 100ms s required after power-up, followed by two AUTO REFRESH commands, before proper device operation s ensured. (VCC must be
powered up simultaneously.) The two AUTO REFRESH command wake-ups should be repeated any time the tREF refresh requirement s exceeded.
4. VIH overshoot: VIH (MAX) = VCC + 2V for a pulse width
≤
3ns, and the pulse width cannot be greater than one third of the cycle rate. VIL undershoot: VIL
(MIN) = -2V for a pulse width
≤
3ns.
5. Guaranteed by design, but not tested.