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參數資料
| 型號： | WEDPNF8M721V-1015BI |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| 中文描述： | 8Mx72同步DRAM 8MB閃存的混合模塊多芯片封裝 |
| 文件頁數： | 23/42頁 |
| 文件大小： | 1276K |
| 代理商： | WEDPNF8M721V-1015BI |
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White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
WEDPNF8M721V-XBX
sector to be erased, and the sector erase command, which
in turn invokes the Embedded Erase algorithm. Table 7
shows the address and data requirements for the sector
erase command sequence.
The device does not equire the system to preprogram the
memory prior to erase. The Embedded Erase algorithm au-
tomatically programs and verifies the entire memory for an
all zero data pattern prior to electrical erase. The system is
not required to provide any controls or timings during these
operations.After the command sequence is written, a sec-
tor erase time-out of 50μs begins. During the time-out pe-
riod, additional sector addresses and sector erase com-
mands may be written. Loading the sector erase buffer may
be done in any sequence, and the number of sectors may
be from one sector to all sectors. The time between these
additional cycles must be less than 50μs, otherwise the last
address and command might not be accepted, and era-
sure may begin. It is recommended that processor inter-
rupts can be re-enabled after the last Sector Erase com-
mand is written. If the time between additional sector erase
commands can be assumed to be less than 50μs, the sys-
tem need not monitor FD3.Any command other than the
Sector Erase or Erase Suspend during the time-out
period resets the device to reading array data. The
system must rewrite the command sequence and any ad-
ditional sector addresses and commands.
The system can monitor FD3 to determine if the sector erase
timer has timed out. See the “FD3: Sector Erase Timer” sec-
tion. The time-out begins from the rising edge of the final
FWE pulse in command sequence.
Once the sector erase operation has begun, only the Erase
Suspend command is valid. All other command is valid. All
other commands are ignored. Note that a hardware reset
during the sector erase operation. The Sector Erase com-
mand sequence should be reinitiated once the device has
returned to reading array data, to ensure data integrity.
When the Embedded Erase algorithm is complete, the de-
vice returns to reading array data and addresses are no
longer latched. The system can determine the status of the
erase operation by using FD7, FD6, or FD2, or RY/BY1. See
“Write Operation Status” for information on these status bits.
Figure 7 illustrates the algorithm for the erase operation. See
the Erase/Program Operations tables in the “Flash AC Charac-
teristics” for parameters, and to Figure 13 for timings diagram.
ERASE SUSPEND/ERASE RESUME
COMMAND SEQUENCE
The Erase Suspend command allows the system to interrupt
a sector erase operation and then read data from, or pro-
gram data to, any sector not selected for erasure. This com-
mand is valid only during the sector erase operation, includ-
ing the 50μs time-out period during the sector erase com-
mand sequence. The Erase Suspend command is ignored if
written during the chip erase operation or Embedded Pro-
gram algorithm. Writing the Erase Suspend command during
the Sector Erase time-out immediately terminates the time-
out period and suspends the erase operation. Addresses
are “don't cares” when writing the Erase Suspend command.
When the Erase Suspend command is written during a sec-
tor erase operation, the device requires a maximum of 20μs
to suspend the erase operation. However, when the Erase
Suspend command is written during the sector erase time-
out, the device immediately terminates the time-out period
and suspends the erase operation.
After the erase operation has been suspended, the system
can read array data from or program data to any sector not
selected for erasure. (The device “erase suspends” all sec-
tors selected for erasure.) Normal read and write timings
and command definitions apply. Reading at any address
within erase-suspended sectors produces status data on
FD7-0. The system can use FD7, or FD6, and FD2 together,
to determine if a sector is actively erasing or is erase sus-
pended. See "Write Operation Status" for information on
these status bits.
After an erase-suspended program operation is complete,
the system can once again read array data within non-sus-
pended sectors. The system can determine the status of
the program operation using the FD7 or FD6 status bits, just
as in the standard program operation. See the “Write Op-
eration Status” for more information.
The system may also write the autoselect command se-
quence when the device is in the Erase Suspend mode.
The device allows reading autoselect codes even at ad-
dresses within erasing sectors, since the codes are not
stored in the memory array. When the device exits the
autoselect mode, the device reverts to the Erase Suspend
mode, and is ready for another valid operation.
The system must write the Erase Resume command (address
bits are “don't care”) to exit the erase suspend mode and
continue the sector erase operation. Further writes of the
Resume command are ignored. Another Erase Suspend com-
mand can be written after the device has resumed erasing.
相關PDF資料 |
PDF描述 |
|---|---|
| WEDPNF8M721V-1015BM | 8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M721V-1210BC | 8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M721V-1210BI | 8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M721V-1210BM | 8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M721V-1212BI | 8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
相關代理商/技術參數 |
參數描述 |
|---|---|
| WEDPNF8M721V-1015BM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M721V-1210BC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M721V-1210BI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M721V-1210BM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M721V-1212BC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
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