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參數(shù)資料
| 型號(hào)： | WEDPNF8M721V-1015BI |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| 中文描述： | 8Mx72同步DRAM 8MB閃存的混合模塊多芯片封裝 |
| 文件頁數(shù)： | 25/42頁 |
| 文件大小： | 1276K |
| 代理商： | WEDPNF8M721V-1015BI |
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White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
WEDPNF8M721V-XBX
F
IG
. 8 D
ATA
P
OLLING
A
LGORITHM
1. FD7 should be rechecked even f FD5 = 1 because FD7 may change
simultaneously with FD5.
WRITE OPERATION STATUS
The device provides several bits to determine the status of
a write operation: FD2, FD3, FD5, FD6, and FD7. Table 8 and
the following subsections describe the functions of these
bits. FD7, RY/BY1, and FD6 each offer a method for deter-
mining whether a program or erase operation is complete
or in progress. These bits are discussed first.
FD7: D
ATA
P
OLLING
The Data Polling bit, FD7, indicates to the host system
whether an Embedded Algorithm is in progress or com-
pleted, or whether the device is in Erase Suspend Data Poll-
ing valid after the rising edge of the final FWE pulse in the
program or erase command sequence.
During the Embedded Program algorithm, the device out-
puts on FD7 the complement of the datum programmed to
FD7. This FD7 status also applies to programming during Erase
Suspend. When the Embedded Program algorithm is com-
plete, the device outputs the datum programmed to FD7.
The system must provide the program address to read valid
status information on FD7. If a program address falls within a
protected sector, Data Polling on FD7 is active for approxi-
mately 1μs, then the device returns to reading array data.
During the Embedded Erase algorithm, Data Polling produces
a “0” on FD7. When the Embedded Erase algorithm is com-
plete, or if the device enters the Erase Suspend mode, Data
Polling produces a “1” on FD7. This analogous to the
complement/true datum output described for the Embed-
ded Program algorithm: the erase function changes all the
bits in a sector to “1”; prior to this, the device outputs the
“complement,” or “0.” The system must provide an address
within any of the sectors selected for erasure to read valid
status information on FD7.
After an erase command sequence is written, if all sectors
selected for erasing are protected, Data Polling on FD7 is
active for approximately 100μs, then the device returns to
reading array data. If not all selected sectors are protected,
the Embedded Erase algorithm erases the unprotected sec-
tors, and ignores the selected sectors that are protected.
When the system detects FD7 has changed from the
complement to true data, it can read valid data at FD7-0 on
the following read cycles. This because FD7 may change
asynchronously with FD0-6 while Flash Output Enable (FOE)
is asserted low. Figure 14, Data Polling timings (During Em-
bedded algorithms), in the “Flash AC characteristics” sec-
tion illustrates this.
Table 8 shows the outputs for Data Polling on FD7. Figure 8
shows the Data Polling algorithm.
VA = Byte address for programming
= Any of the sector addresses within the
sector being erased during sector erase
operation
= Valid address equals any non-protected
sector group address during chip erase
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| WEDPNF8M721V-1015BM | 8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M721V-1210BC | 8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M721V-1210BI | 8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M721V-1210BM | 8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M721V-1212BI | 8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| WEDPNF8M721V-1015BM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M721V-1210BC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M721V-1210BI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M721V-1210BM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M721V-1212BC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
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