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參數資料
| 型號： | WEDPNF8M721V-1212BI |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| 中文描述： | 8Mx72同步DRAM 8MB閃存的混合模塊多芯片封裝 |
| 文件頁數： | 11/42頁 |
| 文件大小： | 1276K |
| 代理商： | WEDPNF8M721V-1212BI |
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White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
WEDPNF8M721V-XBX
vents unwanted commands from being registered during
idle or wait states. Operations already in progress are not
affected.
LOAD MODE REGISTER
The Mode Register is loaded via inputs A0-11. See Mode
Register heading in the Register Definition section. The LOAD
MODE REGISTER command can only be issued when all
banks are idle, and a subsequent executable command
cannot be issued until tMRD is met.
ACTIVE
The ACTIVE command is used to open (or activate) a row in
a particular bank for a subsequent access. The value on the
BA0, BA1 inputs selects the bank, and the address pro-
vided on inputs A0-11 selects the row. This row remains
active (or open) for accesses until a PRECHARGE command
is issued to that bank. A PRECHARGE command must be
issued before opening a different row in the same bank.
READ
The READ command is used to initiate a burst read access
to an active row. The value on the BA0, BA1 inputs selects
the bank, and the address provided on inputs A0-8 selects
the starting column location. The value on input A10 deter-
T
ABLE
3 T
RUTH
T
ABLE
- C
OMMANDS
A
ND
DQM O
PERATION
(N
OTE
1)
NAME (FUNCTION)
COMMAND INHIBIT (NOP)
NO OPERATION (NOP)
ACTIVE (Select bank and activate row) ( 3)
READ (Select bank and column, and start READ burst) (4)
WRITE (Select bank and column, and start WRITE burst) (4)
BURST TERMINATE
PRECHARGE (Deactivate row in bank or banks) ( 5)
AUTO REFRESH or SELF REFRESH (Enter self refresh mode) (6, 7)
LOAD MODE REGISTER (2)
Write Enable/Output Enable (8)
Write Inhibit/Output High-Z (8)
NOTES:
1. CKE s HIGH for all commands shown except SELF REFRESH.
2. A0-11 define the op-code written to the Mode Register
3. A0-11 provide row address, and BA0, BA1 determine which bank s made active.
4. A0-8 provide column address; A10 HIGH enables the auto precharge feature (nonpersistent), while A10 LOW disables the auto precharge feature; BA0, BA1
determine which bank s being read from or written to.
5. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks precharged and BA0, BA1 are “Don’t Care.”
6. This command s AUTO REFRESH f CKE s HIGH; SELF REFRESH f CKE s LOW
7. nternal refresh counter controls row addressing; all nputs and /Os are “Don’t Care” except for CKE.
8. Activates or deactivates the /Os during WRITEs (zero-clock delay) and READs (two-clock delay).
CS
H
L
L
L
L
L
L
L
L
–
–
RAS
X
H
L
H
H
H
L
L
L
–
–
CAS
X
H
H
L
L
H
H
L
L
–
–
WE
X
H
H
H
L
L
L
H
L
–
–
DQM
X
X
X
L/H
8
L/H
8
X
X
X
X
L
H
ADDR
X
X
Bank/Row
Bank/Col
Bank/Col
X
Code
X
Op-Code
–
–
I/Os
X
X
X
X
Valid
Active
X
X
X
Active
High-Z
mines whether or not AUTO PRECHARGE is used. If AUTO
PRECHARGE is selected, the row being accessed will be
precharged at the end of the READ burst; if AUTO
PRECHARGE is not selected, the row will remain open for
subsequent accesses. Read data appears on the I/Os sub-
ject to the logic level on the DQM inputs two clocks earlier.
If a given DQM signal was registered HIGH, the correspond-
ing I/Os will be High-Z two clocks later; if the DQM signal
was registered LOW, the I/Os will provide valid data.
WRITE
The WRITE command is used to initiate a burst write access
to an active row. The value on the BA0, BA1 inputs selects
the bank, and the address provided on inputs A0-8 se-
lects the starting column location. The value on input A10
determines whether or not AUTO PRECHARGE is used. If
AUTO PRECHARGE is selected, the row being accessed will
be precharged at the end of the WRITE burst; if AUTO
PRECHARGE is not selected, the row will remain open for
subsequent accesses. Input data appearing on the I/Os is
written to the memory array subject to the DQM input logic
level appearing coincident with the data. If a given DQM
signal is registered LOW, the corresponding data will be
written to memory; if the DQM signal is registered HIGH,
the corresponding data inputs will be ignored, and a WRITE
will not be executed to that byte/column location.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| WEDPNF8M721V-1212BM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M721V-1215BC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M721V-1215BI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M721V-1215BM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M721V-XBX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
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