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參數資料
| 型號： | WEDPNF8M721V-1212BI |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| 中文描述： | 8Mx72同步DRAM 8MB閃存的混合模塊多芯片封裝 |
| 文件頁數： | 7/42頁 |
| 文件大小： | 1276K |
| 代理商： | WEDPNF8M721V-1212BI |
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White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
WEDPNF8M721V-XBX
SDRAM DESCRIPTION
The 64MByte (512Mb) SDRAM is a high-speed CMOS, dy-
namic random-access ,memory using 5 chips containing
134, 217, 728 bits. Each chip is internally configured as a
quad-bank DRAM with a synchronous interface. Each of the
chip’s 33,554,432-bit banks is organized as 4,096 rows by
512 columns by 16 bits.
Read and write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue for a pro-
grammed number of locations in a programmed sequence.
Accesses begin with the registration of an ACTIVE com-
mand, which is then followed by a READ or WRITE com-
mand. The address bits registered coincident with the AC-
TIVE command are used to select the bank and row to be
accessed (BA0, BA1 select the bank; A0-11 select the row).
The address bits registered coincident with the READ or
WRITE command are used to select the starting column lo-
cation for the burst access.
The SDRAM provides for programmable READ or WRITE burst
lengths of 1, 2, 4 or 8 locations, or the full page, with a
burst terminate option. An AUTO PRECHARGE function may
be enabled to provide a self-timed row precharge that is
initiated at the end of the burst sequence.
The 64MB SDRAM uses an internal pipelined architecture to
achieve high-speed operation. This architecture is compat-
ible with the 2n rule of prefetch architectures, but it also
allows the column address to be changed on every clock
cycle to achieve a high-speed, fully random access.
Precharging one bank while accessing one of the other three
banks will hide the precharge cycles and provide seam-
less, high-speed, random-access operation.
The 64MB SDRAM is designed to operate in 3.3V, low-
power memory systems. An auto refresh mode is provided,
along with a power-saving, power-down mode.
All inputs and outputs are LVTTL compatible. SDRAMs offer
substantial advances in DRAM operating performance, in-
cluding the ability to synchronously burst data at a high data
rate with automatic column-address generation, the ability
to interleave between internal banks in order to hide
precharge time and the capability to randomly change col-
umn addresses on each clock cycle during a burst access.
SDRAM FUNCTIONAL DESCRIPTION
Read and write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue for a pro-
grammed number of locations in a programmed sequence.
ICC S
PECIFICATIONS
A
ND
C
ONDITIONS
(N
OTES
1,2,3,4)
(VCC = +3.3V ±0.3V; TA = -55°C
TO
+125°C)
Parameter/Condition
SDRAM Operating Current: Active Mode;
Burst = 2; Read or Write; t
RC
= t
RC
(min); CAS latency = 3 (5, 6, 7); FCS = High
SDRAM Standby Current: Active Mode; CKE = HIGH; CS = HIGH; FCS = High;
All banks active after t
RCD
met; No accesses in progress (5, 7, 8)
SDRAM Operating Current: Burst Mode; Continuous burst; FCS = High
Read or Write; All banks active; CAS latency = 3 (5, 6, 7)
SDRAM Self Refresh Current; FCS = High (14)
Symbol
Max
Units
I
CC1
750
mA
I
CC3
250
mA
I
CC4
750
mA
I
CC7
10
mA
Flash V
CC
Active Current for Read : FCS = V
IL
, FOE = V
IH
, f = 5MHz (9), CS = High, CKE = Low
I
FCC1
32
mA
Flash V
CC
Active Current for Program or Erase: FCS = V
IL
, FOE = V
IH,
CS = High, CKE = Low
I
FCC2
50
mA
Standby Current: V
CC
= 3.6 Max, FCS = V
IH,
CS = High, CKE = Low
I
CC3
20
mA
NOTES:
1. All voltages referenced to VSS.
2. An nitial pause of 100ms s required after power-up, followed by two
AUTO REFRESH commands, before proper device operation s ensured. (VCC
must be powered up simultaneously.) The two AUTO REFRESH command
wake-ups should be repeated any time the tREF refresh requirement s
exceeded.
3. AC timing and CC tests have VIL = 0V and VIH = 3V with timing referenced
to 1.5V crossover point.
4. CC specifications are tested after the device s properly nitialized.
5. CC s dependent on output oading and cycle rates. Specified values are
obtained with minimum cycle time and the outputs open.
6. The CC current will decrease as the CAS atency s reduced. This s due to
the fact that the maximum cycle rate s slower as the CAS atency s reduced.
7. Address transitions average one transition every two clocks.
8. Other nput signals are allowed to transition no more than once every two
clocks and are otherwise at valid VIH or VIL evels.
9. The CC current isted ncludes both the DC operating current and the
frequency dependent component (at 5 MHz). The frequency component
typically s ess than 8 mA/MHz, with OE at VIH.
10. CC active while Embedded Algorithm (program or erase) s n progress.
11. Maximum CC specifications are tested with VCC = VCC Max.
12. Automatic sleep mode enables the ow power mode when addressed
remain stable for tacc + 30 ns.
13. SDRAM nactive and n Power Down mode, all banks dle.
14. Self refresh available n commercial and ndustrial temperatures only.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| WEDPNF8M721V-1212BM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M721V-1215BC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M721V-1215BI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M721V-1215BM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M721V-XBX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
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