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參數(shù)資料
| 型號(hào)： | WEDPNF8M721V-1212BI |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| 中文描述： | 8Mx72同步DRAM 8MB閃存的混合模塊多芯片封裝 |
| 文件頁(yè)數(shù)： | 24/42頁(yè) |
| 文件大小： | 1276K |
| 代理商： | WEDPNF8M721V-1212BI |
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White Electronic Designs Corporation Phoenix AZ (602) 437-1520
White Electronic Designs
WEDPNF8M721V-XBX
LEGEND:
X = Don't Care
RA = Address of the memory ocation to be read.
RD = Data read from ocation RA during read operation.
PA = Address of the memory ocation to be programmed. Addresses are atched on the falling edge of the FWE or FCS pulse, whichever occurs first.
PD = Data to be programmed at ocation PA. Data s atched on the rising edge of FWE or FCS pulse, whichever occurs first.
SA = Address of the sector to be erased. The combination of FA18-12 will uniquely select any sector
NOTES:
1. Bus operations are defined n Table 3.
2. All values are n hexadecimal.
3. Except when reading array or autoselect data, all bus cycles are write operations.
4. Address bits FA18-11 = don’t care for unlock and command cycles, unless PA or SA s required.
5. No unlock or command cycles required when reading array data.
6. The Reset command s required to return to reading array data when device s n the autoselect mode, or f FD5 goes high (while the device s providing status data).
7. The fourth cycle of the autoselect command sequence s a read cycle.
8. The data s 00h for an unprotected sector and 01h for a protected sector
9. The Unlock Bypass command s required prior to the Unlock Bypass Program command.
10. The Unlock Bypass Reset command s required to return to reading array data when the device s n the Unlock Bypass mode.
11. The system may read and program n non-erasing sectors, or enter the autoselect mode, when n the Erase Suspend mode. The Erase Suspend command s valid
only during a sector erase operation.
12. The Erase Resume command s valid only during the Erase Suspend mode.
13. Data bots FD8-15 are don’t cares for unlock and command cycles.
T
ABLE
7 - C
OMMAND
D
EFINITIONS
Bus Cycles (Notes 2, 3, 4, 13)
First Bus
Cycle
Second Bus
Cycle
Third Bus
Cycle
Fourth Bus
Cycle
Fifth Bus
Cycle
Sixth Bus
Cycle
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Read (Note 5)
1
RA
RD
Reset (Note 6)
Device ID,
Bottom Boot Block
A
1
XXX
F0
Byte
Word
4
AAA
555
AA
555
2AA
55
AAA
555
90
X02
X01
5B
225B
Byte
4
AAA
AA
555
55
AAA
90
(SA)
X04
(SA)
X02
XX00
01
XX00
XX01
Word
555
2AA
555
Program
Byte
Word
4
AAA
555
AA
555
2AA
55
AAA
555
A0
PA
PD
Unlock Bypass
Byte
Word
3
AAA
555
AA
555
2AA
55
AAA
555
20
Unlock Bypass Program (Note 9)
2
XXX
A0
PA
PD
Unlock Bypass Reset (Note10) 2
XXX
90
PA
00
Chip Erase
Byte
Word
6
AAA
555
AA
555
2AA
55
AAA
555
80
AAA
555
AA
555
2AA
55
AAA
555
10
Sector Erase
Byte
Word
6
AAA
555
AA
555
2AA
55
AAA
555
80
AAA
555
AA
555
2AA
55
SA
30
Erase Suspended (Note 11)
1
XXX
B0
Erase Resume (Note 12)
1
XXX
30
Bus
Write
Cycles
Req'd
Command
Sequence
(Note 1)
Sector Protect
Verify (Note 7,8)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| WEDPNF8M721V-1212BM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M721V-1215BC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M721V-1215BI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M721V-1215BM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M721V-XBX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
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