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參數(shù)資料
| 型號： | WEDPNF8M721V-1212BI |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| 中文描述： | 8Mx72同步DRAM 8MB閃存的混合模塊多芯片封裝 |
| 文件頁數(shù)： | 15/42頁 |
| 文件大?。?/td> | 1276K |
| 代理商： | WEDPNF8M721V-1212BI |
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White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
WEDPNF8M721V-XBX
both read and write functions. Internally generated and regu-
lated voltages are provided for the program and erase op-
erations.
The device is entirely command set compatible with the
JEDEC Single-Power-Supply Flash Standard. Commands are
written to the command register using standard micropro-
cessor write timings. Register contents serve as input to an
internal state-machine that controls the erase and program
circuitry. Write cycles also internally latch addresses and data
needed for the programming circuitry. Write cycles also in-
ternally latch addresses abd data needed for the program-
ming and erase operations. Reading data out of the device
is similar to reading from other Flash or EPROM devices.
Device programming occurs by executing the program com-
mand sequence. This initiates the Embedded Program al-
gorithm – an internal algorithm that automatically times the
program pulse widths and verifies proper cell margin. The
Unlock Bypass mode faciclitates faster programming times
by requiring only two write cycles to program data instead
of four.
Device erasure occurs by executing the erase command
sequence. This initiates the Embedded Erase algorithm –
an internal algorithm that automaticaally preprograms the
array (if it is not already programmed) before executing the
erase operation. During erase, the device automatically times
the erase pulse widths and verifies proper cell margin.
The host system can detect whether as program or erase
operation is complete by observing the RY/BY1 pin, or by
reading FD7 (Data Polling) and FD6 (toggle) status bits. After
a program or erase cycle has been completed, the device
is ready to read array data or accept another command.
The Sector Erase Architecture allows memory sectors to
be erased and reprogrammed without affecting the data
contents of other sectords. The device is fully erased when
shipped from the factory.
Hardware Data Protection measures include a low Vcc de-
tector that automatically inhibits write operations during
power transitions. The Hardware Sector Protection feature
disables bith program and erase operations in any combi-
nation of sectors of memory. This can be achieved in-sys-
tem or via programming equipment.
The Hardware Sector Protection feature disables both pro-
gram and erase operations in any combination of sectors
of memory. This can be achieved in-system or via program-
ming equipment.
The Erase Suspend feature enables the user to put erase
on hold for any period of time to read data from, or proThe
gram data to, any sector that is not selected for erasure.
True background erase can thus be achieved.
The Hardware Rest (RST) pin terminates any operation in
progress and resets the internal state machine to reading
array data. The RST pin may be tied to the reset circuitry. A
system reset would thus also reset the device, enabling the
system microprocessor to read the boot-up firmware from
Flash memory.
The device offers two power saving features. When ad-
dresses have been stable for specified amount of time, the
device enters the automatic sleep mode. The system can
also place the device into the standby mode. Power con-
sumption is greatly reduced in both these modes
DEVICE BUS OPERATIONS
This section describes the requirements and use of the
device bus operations, which are initiated through the in-
ternal command register. The command register itself does
not occupy any addressable memory location. The register
is composed of latches that store the commands, along
with the address and data information needed to execute
the command. The contents of the register serve as inputs
to the internal state machine. The state machine outputs
dictate the function of the device. Table 4 lists the device
bus operations, the inputs and control levels required, and
the resulting output. The following subsections describe
each of these operations in further detail.
WORD/BYTE CONFIGURATION
The BYTE1 pin controls whether the device data I/O pins
FDO-15 operate in the byte or word configuration. If the
BYTE1 pin is set at logic ‘1’, the device is in word configu-
ration, FD0-15 are active and controlled by FCS and FOE.
If the BYTE1 pin is set at logic ‘0’, the device is in byte con-
figuration, and only data I/O pins FD0-7 are active and con-
trolled by FCS and FOE. The data I/O pins FD8-14 are tri
stated, and the FD15 pin is used as an input for the LSB (FA-
1) address function.
REQUIREMENTS FOR READING
ARRAY DATA
To read array data from the outputs, the system must drive
the FCS and FOE pins to VIL. FCS is the power control and
selects the device. FOE is the output control and gates ar-
ray data to the output pins. FWE should remain at VIH. The
BYTE1 pin determines whether the device outputs array data
in words or bytes.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| WEDPNF8M721V-1212BM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M721V-1215BC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M721V-1215BI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M721V-1215BM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M721V-XBX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
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