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參數(shù)資料
| 型號： | W89C940 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | ELANC-PCI (TWISTED-PAIR ETHER-LAN CONTROLLER WITH PCI INTERFACE) |
| 中文描述： | ELANC -的PCI（雙絞線醚局域網(wǎng)控制器帶有PCI接口） |
| 文件頁數(shù)： | 17/61頁 |
| 文件大小： | 353K |
| 代理商： | W89C940 |
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W89C940
17
Device I.D. Register
The device I.D. identifies the particular device. This identifier is allocated by the vendor.The content of this
register will be updated after power on by the EEPROM load operation. The device ID should be programmed
into the word with 0AH address of the EEPROM for power on auto loading.
Command Register
Bit Location
0
Attribute
R/W
Description
This bit controls the I/O space access response of W89C940. A
value of "0" will disables the W89C940 response. A value of "1"
allows the W89C940 to respond to I/O space accesses.
This bit controls the memory space access response of W89C940.
A value of "0" will disables the W89C940 response. A value of "1"
allows the W89C940 to respond to memory space accesses.
The W89C940 do not support PCI bus master function. This bit is
fixed to "0".
The W89C940 do not support the special cycle operation. This bit
is fixed to "0"
The W89C940 do not support the memory write cycle and the
invalidate command. This bit is fixed to "0".
The W89C940 is not a VGA compatible device. This bit is fixed to
"0".
This bit controls the parity error response of W89C940. A value of
"0" will force the W89C940 ignore a parity error. A value of "1"
allows the W89C940 to take a normal action when a parity error is
detected. This bit will be reset after power ON.
The W89C940 do not support data stepping function and this bit is
fixed to "0" always.
This bit is an enable bit for W89C940 internal SERR# driver. A
value of "0" will disables the internal SERR# driver. A value of "1"
enables the internal SERR# driver.
All of these bits are fixed to "0" internally. And no specific function
are related to these bits.
1
R/W
2
R
3
R
4
R
5
R
6
R/W
7
R
8
-
9~15
R
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