- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄22044 > LFX200EB-04FN256I (Lattice Semiconductor Corporation)IC FPGA 200K GATES 256-BGA PDF資料下載
參數(shù)資料
| 型號(hào)： | LFX200EB-04FN256I |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁(yè)數(shù)： | 31/119頁(yè) |
| 文件大小： | 0K |
| 描述： | IC FPGA 200K GATES 256-BGA |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 系列： | ispXPGA® |
| 邏輯元件/單元數(shù)： | 2704 |
| RAM 位總計(jì)： | 113664 |
| 輸入/輸出數(shù)： | 160 |
| 門數(shù)： | 210000 |
| 電源電壓： | 2.3 V ~ 3.6 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 105°C |
| 封裝/外殼： | 256-BGA |
| 供應(yīng)商設(shè)備封裝： | 256-FPBGA（17x17） |
| 其它名稱： | 220-1239 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)當(dāng)前第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)
Lattice Semiconductor
ispXPGA Family Data Sheet
15
Figure 17. ispXPGA PLL_RST and PLL_FBK Generation
Clock Routing
The Global Clock Lines (GCLK) have two sources, their dedicated pins and the sysCLOCK circuit. Figure 18 illus-
trates the generation of the Global Clock Lines.
Figure 18. Global Clock Line Generation
sysIO Capability
All the ispXPGA devices have eight sysIO banks, where each bank is capable of supporting multiple I/O standards.
Each sysIO bank has its own I/O supply voltage (VCCO) and reference voltage (VREF) resources allowing each
bank complete independence from the others. Each I/O is individually configurable based on the bank’s VCCO and
VREF settings. In addition, each I/O has configurable drive strength, weak pull-up, weak pull-down, or a bus-keeper
latch. Table 4 lists the number of I/Os supported per bank in each of the ispXPGA devices. In addition, 5V tolerant
inputs are specified within an I/O bank that is connected to VCCO of 3.0V to 3.6V for LVCMOS 3.3, LVTTL and PCI
interfaces.
The TOE, JTAG TAP pins, PROGRAM, CFG0 and DONE pins of the ispXPGA device are the only pins that do not
have the sysIO capabilities. The TOE and CFG0 pins operate off the VCC of the device, supporting only the LVC-
MOS standard corresponding to the device supply voltage. The TAP pins have a separate supply voltage (VCCJ),
which determines the LVCMOS standard corresponding to that supply voltage.
There are three classes of I/O interface standards that are implemented in the ispXPGA devices. The first is the un-
terminated, single-ended interface. It includes the 3.3V LVTTL standard along with the 1.8V, 2.5V, and 3.3V LVC-
MOS interface standards. Additionally, PCI and AGP-1X are subsets of this type of interface.
I/O/PLL_RST
I/O/PLL_FBK
From Routing
From Clock Net
To PLL
PLL0
GCLK0
CLK_OUT0
SEC_OUT0
PLL1
CLK_OUT1
SEC_OUT1
GCLK1
PLL2
CLK_OUT2
SEC_OUT2
GCLK2
PLL3
CLK_OUT3
SEC_OUT3
GCLK3
PLL7
GCLK7
CLK_OUT7
SEC_OUT7
PLL6
CLK_OUT6
SEC_OUT6
GCLK6
PLL5
CLK_OUT5
SEC_OUT5
GCLK5
PLL4
CLK_OUT4
SEC_OUT4
GCLK4
CLK0
CLK1
CLK2
CLK3
CLK7
CLK6
CLK5
CLK4
From Routing
DEVICES
DISCONTINUED
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| NCP500SN26T1 | IC REG LDO 2.6V .15A 5TSOP |
| RGM36DTMS-S189 | CONN EDGECARD 72POS R/A .156 SLD |
| RMM36DTMS-S189 | CONN EDGECARD 72POS R/A .156 SLD |
| VE-BWW-CV-F3 | CONVERTER MOD DC/DC 5.5V 150W |
| TAWD336K016R0600 | CAP TANT 33UF 16V 10% 2917 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LFX200EB-04FN516C | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 E-Ser210K Gt ispJTA G 2.5/3.3V -4 Spd RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| LFX200EB-04FN516I | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 E-Ser210K Gt ispJTA G 2.5/3.3V -4 Spd I RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| LFX200EB-05F256C | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 210K Gates, 160 I/O 2.5/3.3V, -5 speed RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| LFX200EB-05F516C | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 210K 208 I/O ispJTAG RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| LFX200EB-05FH516C | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 Use LFX200EB-05F516C RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。