
Preliminary W79E217A Data Sheet
Publication Release Date: December 14, 2007
- 127 -
Revision A3.0
The trigger option is programmable through CCTx [1:0] (CAPCON0). It supports positive edge,
negative edge and both edge triggers. Each capture module consists of an enable, ICEN0~2. [Note:
x=0, 1, 2 for capture 0, 1, 2 block].
Capture blocks are triggered by external pins IC0, IC1 and IC2, respectively. If ICENx is enabled, each
time the external pin triggers, the content of the free running 16 bits counter, TL3 & TH3 (from Timer 3
block) will be captured/transferred into the corresponding capture registers, CCLx and CCHx. This
action also causes the corresponding CPTFx flag bit in CAPCON1 to be set, and generate an interrupt
(if enabled by ECPTF bit in SFR, EIE1.4). The CPTF0-2 flags are logical “OR” to the interrupt module.
Input Capture 0~2 share one interrupt named Capture Interrupt. Flag is set by hardware and cleared
by software.
Setting the T3CR bit (T3MOD.3), will allow hardware to reset timer 3 automatically after the value of
TL3 and TH3 have been captured. Priority is given to T3CR to reset counter after capture the timer
value into the capture register. When
RL3
CMP/
= 0 (reload mode, with T3CR=0 and ENLD=1),
RCAP3 will be loaded into Timer 3 counter upon overflow. While the rest of the condition of
combination of setting for T3CR and ENLD will reset the counter to 0000H.
Noise
Filter
CPTF0
CCL0
CCH0
Capture 0 Block
[00]
[01]
[10]
ICEN0
IC0
CCT0[1:0]
ENF0
[1]
Capture 1
Block
Capture 2
Block
(Note)
IC1
IC2
CPTF1
CPTF2
With
Schmitt
Trigger
Fosc
DIV by
1,4,16,32
TL3
TH3
RCAP3L
RCAP3H
00
01
10
11
TR3
CCDIV[1:0]
CPTF0
CPTF1
CPTF2
CCLD[1:0]
CMP/RL3
ENLD
Timer 3 Block
=
0
1
TF3
CMP/RL3
TMF3
TMF3
CMP/RL3
TOVF3
Reset
Timer3
T3CR
CPTF0
Note:TOVF3 = Timer 3 overflow
TMF3 = Internal Timer 3 Flag signal.
Input Capture 2 block (refer to Figure 15-3).
Figure 15-2: Timer3/Capture/Compare/Reload modules