
Preliminary W79E217A Data Sheet
Publication Release Date: December 14, 2007
- 164 -
Revision A3.0
DRSS
SSOE
MASTER MODE
SLAVE MODE
0
0
SS
input ( With Mode Fault )
SS
Input ( Not affected by SSOE )
0
1
Reserved
SS
Input ( Not affected by SSOE )
1
0
SS
General purpose I/O ( No Mode Fault )
SS
Input ( Not affected by SSOE )
1
1
SS
output ( No Mode Fault )
SS
Input ( Not affected by SSOE )
During master mode (with SSOE=DRSS= 0), mode fault will be set if
SS
pin is detected low. When
mode fault is detected hardware will clear MSTR bit and SPE bit in the meantime it will also generated
interrupt request, if ESPI is enabled.
Figure 18-10: SPI interrupt request
18.3.5 SPI I/O pins mode
When SPI is disabled (SPE = 0) the corresponding I/O is following the original setting and act as a
normal I/O. In the case of SPI is enabled (SPE = 1) the SPI pins I/O mode follow the below table. For
SS
pin it is always at Quasi-bidirectional mode whether it is configured as master or slave.
MISO
MOSI
CLK
/SS
Master
Input
Output
Output
Output
*:
DRSS=0,SSOE=0
Input: DRSS=1, SSOE=1
Slave
Output
**
during /SS = Low
Else Input mode
Input
Input
Input
Input = Quasi-bidirectional mode
Output = Push-pull mode
Output*
= this output mode in /SS is Quasi-bidirectional output mode. Master needs to detect
mode fault during master outputs /SS low.
Output**
= In SLAVE mode, MISO is in output mode only during the time of
SS
=Low,
otherwise it must keep in input mode (Quasi-bidirectional).