
Preliminary W79E217A Data Sheet
Publication Release Date: December 14, 2007
- 194 -
Revision A3.0
AC Specification, continued
PARAMETER
SYMBOL
VARIABLE
CLOCK
MIN.
VARIABLE
CLOCK
MAX.
UNITS
Port 2 Address to Valid Instr. In
t
AVIV2
3.5t
CLCL
- 20
nS
PSEN
Low to Address Float
t
PLAZ
0
nS
Data Hold After Read
t
RHDX
0
nS
Data Float After Read
t
RHDZ
t
CLCL
- 5
nS
RD
Low to Address Float
t
RLAZ
0.5t
CLCL
- 5
nS
Note:
1. CPU executes the program stored in the internal APFlash at V
DD
=5.0V
2. CPU executes the program stored in the external memory at V
DD
=5.0V
25.3.3 MOVX Characteristics Using Stretch Memory Cycle
PARAMETER
SYMBOL
VARIABLE
CLOCK
MIN.
VARIABLE
CLOCK
MAX.
UNITS
STRECH
Data Access ALE Pulse Width
t
LLHL2
1.5t
CLCL
- 5
2.0t
CLCL
- 5
nS
t
MCS
= 0
t
MCS
>0
Address Hold After ALE Low
for MOVX write
t
LLAX2
0.5t
CLCL
- 5
nS
RD
Pulse Width
t
RLRH
2.0t
CLCL
- 5
t
MCS
- 10
nS
t
MCS
= 0
t
MCS
>0
WR
Pulse Width
t
WLWH
2.0t
CLCL
- 5
t
MCS
- 10
nS
t
MCS
= 0
t
MCS
>0
RD
Low to Valid Data In
t
RLDV
2.0t
CLCL
- 20
t
MCS
- 20
nS
t
MCS
= 0
t
MCS
>0
Data Hold after Read
t
RHDX
0
nS
Data Float after Read
t
RHDZ
t
CLCL
- 5
2.0t
CLCL
- 5
nS
t
MCS
= 0
t
MCS
>0
ALE Low to Valid Data In
t
LLDV
2.5t
CLCL
- 5
t
MCS
+ 2t
CLCL
-
40
nS
t
MCS
= 0
t
MCS
>0
Port 0 Address to Valid Data In
t
AVDV1
3.0t
CLCL
- 20
2.0t
CLCL
- 5
nS
t
MCS
= 0
t
MCS
>0
ALE Low to
RD
or
WR
Low
t
LLWL
0.5t
CLCL
- 5
1.5t
CLCL
- 5
0.5t
CLCL
+ 5
1.5t
CLCL
+ 5
nS
t
MCS
= 0
t
MCS
>0
Port 0 Address to
RD
or
WR
Low
t
AVWL
t
CLCL
- 5
2.0t
CLCL
- 5
nS
t
MCS
= 0
t
MCS
>0