
Preliminary W79E217A Data Sheet
Publication Release Date: December 14, 2007
- 20 -
Revision A3.0
Continued
SYMBOL
DEFINITION
ADD
RESS
MSB
LSB
BIT_ADDRESS,
SYMBOL
RESET
ADCH
ADC CONVERTER RESULT
HIGH BYTE
ADC CONTROL REGISTER
ACCUMULATOR
PWMCON3 3
PWM 6 LOW BITS
REGISTER
PWM 2 LOW BITS
REGISTER
PWMCON1 1
E2H
ADC.9
ADC.8
ADC.7
ADC.6
ADC.5
ADC.4
ADC.3
ADC.2
xxxx xxxxB
ADCCON
ACC
E1H
E0H
ADCEN
(E7)
-
(E6)
ADCEX
(E5)
ADCI
(E4)
ADCS
(E3)
AADR2
(E2)
AADR1 AADR0 0x00 0000B
(E1)
(E0)
0000 0000B
DFH
PWM7B PWM6B PWM5B PWM4B PWM3B PWM2B PWM1B PWM0B 0000 0000B
PWM6L
DEH PWM6.7 PWM6.6 PWM6.5 PWM6.4 PWM6.3 PWM6.2 PWM6.1 PWM6.0 0000 0000B
PWM2L
DDH PWM2.7 PWM2.6 PWM2.5 PWM2.4 PWM2.3 PWM2.2 PWM2.1 PWM2.0 0000 0000B
DCH
PWMRU
N
NVMAD
DRH.7
Load
PWMF
CLRPW
M
NVMAD
DRH.4
PWM6I
PWM4I
PWM2I
PWM0I
0000 0000B
NVMADDRL NVM LOW BYTE ADDRESS
DBH
NVMAD
DRH.6
NVMAD
DRH.5
NVMAD
DRH.3
NVMAD
DRH.2
NVMAD
DRH.1
NVMAD
DRH.8
0000 0000B
PWM0L
PWM 0 LOW BITS
REGISTER
PWM COUNTER LOW
REGISTER
DAH PWM0.7 PWM0.6 PWM0.5 PWM0.4 PWM0.3 PWM0.2 PWM0.1 PWM0.0 0000 0000B
PWMPL
D9H
PWMP.7 PWMP.6 PWMP.5 PWMP.4 PWMP.3 PWMP.2 PWMP.1 PWMP.0 0000 0000B
WDCON
WATCH-DOG CONTROL
D8H
(DF)
-
-
(DE)
POR
-
(DD)
-
-
(DC)
-
-
(DB)
WDIF
-
PWM6.1
1
PWM2.1
1
DIR
NVMDA
T.3
PWM0.1
1
PWMP.1
1
(D3)
RS0
(DA)
WTRF
-
PWM6.1
0
PWM2.1
0
QEIM1
NVMDA
T.2
PWM0.1
0
PWMP.1
0
(D2)
OV
(D9)
EWT
-
(D8)
RWT
STRLD
0100 0000B
WDCON2
WATCH-DOG CONTROL2
PWM 6 HIGH BITS
REGISTER
PWM 2 HIGH BITS
REGISTER
QEI CONTROL REGISTER
D7H
0000 0000B
PWM6H
D6H
-
-
-
-
PWM6.9 PWM6.8 xxxx 0000B
PWM2H
D5H
-
-
-
-
PWM2.9 PWM2.8 xxxx 0000B
QEICON
D4H
-
NVMDA
T.7
-
NVMDA
T.6
-
NVMDA
T.5
DISIDX
NVMDA
T.4
QEIM0
NVMDA
T.1
QEIEN
NVMDA
T.0
xxx0 0000B
NVMDAT
NVM DATA
D3H
0000 0000B
PWM0H
PWM 0 HIGH BITS
REGISTER
PWM COUNTER HIGH
REGISTER
D2H
-
-
-
-
PWM0.9 PWM0.8 xxxx 0000B
PWMPH
D1H
-
-
-
-
PWMP.9 PWMP.8 xxxx 0000B
PSW
PROGRAM STATUS WORD
D0H
(D7)
CY
(D6)
AC
(D5)
F0
(D4)
RS1
(D1)
F1
(D0)
P
0000 0000B
PWM4L
PWM 4 LOW BITS
REGISTER
CFH
PWM4.7 PWM4.6 PWM4.5 PWM4.4 PWM4.3 PWM4.2 PWM4.1 PWM4.0 0000 0000B
PWMCON2 2
TH2
T2 REG. HIGH
TL2
T2 REG. LOW
CEH BKCH
BKPS
BPEN
BKEN
FP1
FP0
PMOD1 PMOD0 0000 0000B
CDH TH2.7
CCH TL2.7
TH2.6
TL2.6
RCAP2H
.6
RCAP2L
.6
HC4
TH2.5
TL2.5
RCAP2H
.5
RCAP2L
.5
HC3
TH2.4
TL2.4
RCAP2H
.4
RCAP2L
.4
HC2
TH2.3
TL2.3
RCAP2H
.3
RCAP2L
.3
T2CR
TH2.2
TL2.2
RCAP2H
.2
RCAP2L
.2
-
TH2.1
TL2.1
RCAP2H
.1
RCAP2L
.1
-
(C9)
TH2.0
TL2.0
RCAP2H
.0
RCAP2L
.0
DCEN
(C8)
0000 0000B
0000 0000B
RCAP2H
T2 CAPTURE LOW
CBH
RCAP2H
.7
RCAP2L
.7
HC5
0000 0000B
RCAP2L
T2 CAPTURE HIGH
CAH
0000 0000B
T2MOD
TIMER 2 MODE
C9H
0000 0xx0B
T2CON
TIMER 2 CONTROL
C8H
(CF)
TF2
(CE)
EXF2
(CD)
RCLK
(CC)
TCLK
(CB)
EXEN2
(CA)
TR2
T
C/
RL2
CP/
0000 0000B
TA
DDIO
TIME ACCESS REGISTER
DISABLE DIGITAL I/O
FAULT SAMPLING TIME
REGISTER
POWER MANAGEMENT
REGISTER
TIMER 3 CONTROL
C7H
C6H
TA.7
DDIO.7
TA.6
DDIO.6
TA.5
DDIO.5
TA.4
DDIO.4
TA.3
DDIO.3
TA.2
DDIO.2
TA.1
DDIO.1 DDIO.0 0000 0000B
TA.0
0000 0000B
FSPLT
C5H
SCMP1
SCMP0
SFP1
SFP0
SFCEN
SFCST
SFCDIR LSBD
0000 0000B
PMR
C4H
-
-
-
-
-
ALEOFF -
DME0
xxxx x0x0B
T3CON
C3H
TF3
-
-
-
-
TR3
-
0xxx x0x0B