
Preliminary W79E217A Data Sheet
Publication Release Date: December 14, 2007
- 23 -
Revision A3.0
Continued
SYMBOL
DEFINITION
ADDR
ESS
83H
82H
81H
MSB
LSB
DPH.7
DPL.7
SP.7
(87)
INT5
BIT_ADDRESS,
SYMBOL
RESET
DPH
DPL
SP
DATA POINTER HIGH
DATA POINTER LOW
STACK POINTER
DPH.6
DPL.6
SP.6
(86)
INT4
DPH.5
DPL.5
SP.5
(85)
INT3
DPH.4
DPL.4
SP.4
(84)
INT2
DPH.3
DPL.3
SP.3
(83)
/SS
DPH.2
DPL.2
SP.2
(82)
SPCLK
DPH.1
DPL.1
SP.1
(81)
MOSI
DPH.0
DPL.0
SP.0
(80)
MISO
0000 0000B
0000 0000B
0000 0111B
P0
PORT 0
80H
1111 1111B
Table 7-2: Special Function Registers
PORT 0
Bit:
7
6
5
4
3
2
1
0
P0.7
P0.6
P0.5
P0.4
P0.3
P0.2
P0.1
P0.0
Mnemonic: P0
Port 0 is an open-drain 8-bit bi-directional I/O port. As an alternate function Port 0 can function as the
multiplexed address/data bus to access off-chip memory. During the time when ALE is high, the LSB
of a memory address is presented. When ALE is low, the port transits to a bi-directional data bus. This
bus is used for reading external ROM and for reading or writing external RAM memory or peripherals.
When used as a memory bus, the port provides active high drivers. The reset condition of Port 0 is tri-
state. Pull-up resistors are required when using Port 0 as an I/O port.
Address: 80h
BIT
NAME
FUNCTION
0
P0.0
MISO: SPI Master In Slave Out.
1
P0.1
MOSI: SPI Master Out Slave In.
2
P0.2
SPCLK: SPI Clock.
3
P0.3
/SS: Slave Select.
4
P0.4
INT2: External Interrupt 2.
5
P0.5
INT3: External Interrupt 3.
6
P0.6
INT4: External Interrupt 4.
7
P0.7
INT5: External Interrupt 5.
STACK POINTER
Bit:
7
6
5
4
3
2
1
0
SP.7
SP.6
SP.5
SP.4
SP.3
SP.2
SP.1
SP.0
Mnemonic: SP
The Stack Pointer stores the Scratch-pad RAM address where the stack begins. In other words it
always points to the top of the stack.
Address: 81h
DATA POINTER LOW
Bit:
7
6
5
4
3
2
1
0
DPL.7
DPL.6
DPL.5
DPL.4
DPL.3
DPL.2
DPL.1
DPL.0
Mnemonic: DPL
This is the low byte of the standard 8032 16-bit data pointer.
Address: 82h