
W88111AF/W88112F
Preliminary/Confidential
ATAPI CD-ROM Decoder & Controller
This specification is subject to change without notice.
Publication Release Date: Aug, 1996
Preliminary/ Confidential Revision A0.1
- 25 -
Decoder Parameter
Updated at the end of sync
Updated by writing CRRL
EDCEN (0Ah.5)
yes
yes
QCEN (0Ah.1)
yes
yes
PCEN (0Ah.0)
yes
yes
ACEN (0Ah.4)
yes
no
BUFEN (0Ah.2)
yes
no
M2RQ (0Bh.3)
yes
no
F2RQ (0Bh.2)
yes
no
MCRQ (0Bh.1)
yes
no
FDIEN (10h.3)
yes
no
MBTC0 - Multi-Block Transfer Control 0 - (read/write 12h)
This register is available for W88111AF only to specify the behavior of multi-block transfer logic. The
host interface supports multi-block transfer without microprocessor intervention by following
sequence:
MBC[4:0]
←
the number of block to be transferred minus 1 (ex. 3)
TBCL (02h), TBCH (03h)
←
the number of bytes/words to be transferred in each block
minus 1 (ex. 1175)
TACL (04h), TACH (05h)
←
the starting point of the block (ex. F4h, FFh)
TBL (24h), TBH (25h)
←
the RAM block number of the first block to be transferred (ex. 5)
ATBLO (34h), ATBLH (35h)
←
the total bytes to be transferred (ex. 9408)
ADTT (17h.4)
←
1
PS: STBCEN (18h.3) should not be set in multi-block transfer operation.
When ADTT is set, host will receive HIRQ, check status, and then start to read data.
After the last bytes/words of one block (except the last one) is read by the host, the following
hardware sequence is executed:
TBCL (02h), TBCH (03h)
←
reload
TACL (04h), TACH (05h)
←
reload
TBL (24h), TBH (25h)
←
auto-increment
MBC[4:0]
←
auto-decrement
TENDb only becomes active at the end of data transfer of the last block.
Bit 7: MBVAb - Multi-Block Counter Valid Flag
This bit is used to indicate that Multi-Block Counter MBC[4:0] is stable enough to be monitored by
microprocessor.