
W88111AF/W88112F
Preliminary/Confidential
ATAPI CD-ROM Decoder & Controller
This specification is subject to change without notice.
Publication Release Date: Aug, 1996
Preliminary/ Confidential Revision A0.1
- 34 -
RAMWR - RAM Write Register - (write 1Eh)
To gain access to external RAM, the microprocessor should first wait for flag UTBY (1Fh.7) to
become low, then set the address through RACL (1Ch), RACH (1Dh), and RACU (2Dh).
Writing data into register RAMWR triggers the following sequence:
Data is transferred from the microprocessor to register RAMWR.
Data is transferred from RAMWR to the RAM located by the address counter.
RACL, RACH, and RACU increases by one
Clear flag UTBY
RAMRD - RAM Read Register - (read 1Eh)
To gain access to external RAM, the microprocessor should first wait for flag UTBY (1Fh.7) to
become low, , then set the address through RACL (1Ch), RACH (1Dh), and RACU (2Dh).
Writing data into register RAMRD triggers the following sequence:
Data previously stored in RAMRD is transferred to the microprocessor.
RAM data located by the address counter is transferred to the RAMRD register.
RACL, RACH, and RACU increases by one
Clear flag UTBY
Note that the first data read from RAMRD is invalid.
HICTL0 - Host Interface Control Register - (write 1Fh)
Bit 7: UDTS - Microprocessor Data Transfer Select
Setting UDTS to high enables microprocessor writes to data registers DF0-DF7(40h-47h) and data
transfers from DF0-DF7 to the host.
Bit 6: UDTT - Microprocessor Data Transfer Trigger
Change from 0 to 1 of UDTT triggers the data transfer from DF0-DF7 to the host. This type of
transfer is efficient for up to 8-byte data transfer. The host will receive data from DF0 to DF7 after
the following sequence.