
W88111AF/W88112F
Preliminary/Confidential
ATAPI CD-ROM Decoder & Controller
This specification is subject to change without notice.
Publication Release Date: Aug, 1996
Preliminary/ Confidential Revision A0.1
- 42 -
Bit 3 : HIRQ - Host Interrupt Request
Set this bit high asserts interrupt at pin HIRQ if the drive is selected and nIEN is enabled in the
ATAPI Device Control Register. HIRQ is also automatically set by the following:
Automatic Packet Transfer sequence (see APKTEN, 18h.7)
Automatic Status Completion sequence (see SCT, 18h.0 and ASCEN, 18h.5)
HIRQ is automatically de-activated by the following:
Chip reset or host reset
Set bit SRST in the ATAPI Device Control Register high
Host issue ATA command while the drive is selected
Host read ATAPI Status Register while the drive is selected
Bit 2: SHIEN - Shadow Command Interrupt Enable
Setting this bit high enables the microprocessor interrupt for the shadow command. Pin UINTb
becomes low-active when SHDC (2Fh.5) becomes high-active if SHIEN is enabled.
Bit 1, 0: Reserved
MISS0 - Miscellaneous Status Register 0 - (read 2Eh)
Bit 5: SRUb - Status Register Updated Flag
This bit becomes high when the ATAPI Status Register is updated by the following:
Microprocessor writes to 37h
Microprocessor triggers DSCT (17h.5)
Microprocessor triggers SCT (17h.0)
Automatic Status Completion occurs if ASCEN (18h.5) is enabled
Reception of A0h command if APKTEN (18h.7) is enabled
Chip reset or host reset
Bit 4: MDRVF - Master Drive Flag
This bit is high if the drive is configured as Master. This bit is low if the drive is configured as
Slave.
Bit 3: HINTF - Host Interrupt Flag
This bit reflects the status of the source of pin HIRQ.
Bit 2: nIEN - Bit nIEN in Device Control Register
This bit reflects the value of bit nIEN in ATAPI Device Control Register.